opcodes/

	* mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
	instructions.  Fix them to use WR_MACC instead of WR_CC and
	add missing RD_MACCs.

2 files changed, 37 insertions, 31 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 35e9633..b021f90 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,11 @@
 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 
+	* mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
+	instructions.  Fix them to use WR_MACC instead of WR_CC and
+	add missing RD_MACCs.
+
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
 	* mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
 
 2013-07-29  Peter Bergner <bergner@vnet.ibm.com>
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 59a63dd..80b555b 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -425,7 +425,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add.s",		"D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1,		0,	0 },
 {"add.d",		"D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,		0,	SF },
 {"add.ob",		"X,Y,Q",	0x7800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"add.ob",		"D,S,Q",	0x4800000b, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"add.ob",		"D,S,Q",	0x4800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"add.ps",		"D,V,T",	0x46c00000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"add.ps",		"D,V,T",	0x45600000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E,		0,	0 },
 {"add.qh",		"X,Y,Q",	0x7820000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
@@ -442,7 +442,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",		"D,S,T",	0x45800000, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		IL2E,		0,	0 },
 {"addu",		"D,S,T",	0x4b00000c, 0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,		IL2F|IL3A,	0,	0 },
 {"alni.ob",		"X,Y,Z,O",	0x78000018, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"alni.ob",		"D,S,T,%",	0x48000018, 0xff00003f,	WR_D|RD_S|RD_T, 	0,		N54,		0,	0 },
+{"alni.ob",		"D,S,T,%",	0x48000018, 0xff00003f,	WR_D|RD_S|RD_T|FP_D, 	0,		N54,		0,	0 },
 {"alni.qh",		"X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"alnv.ps",		"D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		I5_33,		0,	0 },
 {"alnv.ob",		"X,Y,Z,s",	0x78000019, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		SB1,		MX,	0 },
@@ -452,7 +452,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and",			"D,S,T",	0x47c00002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"and",			"D,S,T",	0x4bc00002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"and.ob",		"X,Y,Q",	0x7800000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"and.ob",		"D,S,Q",	0x4800000c, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"and.ob",		"D,S,Q",	0x4800000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"and.qh",		"X,Y,Q",	0x7820000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"andi",		"t,r,i",	0x30000000, 0xfc000000,	WR_t|RD_s,		0,		I1,		0,	0 },
 {"aset",		"\\,~(b)",	0x04078000, 0xfc1f8000,	SM|RD_b|NODS,		0,		0,		MC,	0 },
@@ -559,7 +559,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.eq.s",		"S,T",		0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,		I1,		0,	0 },
 {"c.eq.s",		"M,S,T",	0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32,		0,	0 },
 {"c.eq.ob",		"Y,Q",		0x78000001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"c.eq.ob",		"S,Q",		0x48000001, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"c.eq.ob",		"S,Q",		0x48000001, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"c.eq.ps",		"S,T",		0x46c00032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"c.eq.ps",		"S,T",		0x45600032, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E,		0,	0 },
 {"c.eq.ps",		"M,S,T",	0x46c00032, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33,		0,	0 },
@@ -633,7 +633,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.lt.s",		"S,T",		0x4600003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1,		0,	EE },
 {"c.lt.s",		"M,S,T",	0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32,		0,	0 },
 {"c.lt.ob",		"Y,Q",		0x78000004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"c.lt.ob",		"S,Q",		0x48000004, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"c.lt.ob",		"S,Q",		0x48000004, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"c.lt.ps",		"S,T",		0x46c0003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"c.lt.ps",		"S,T",		0x4560003c, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E,		0,	0 },
 {"c.lt.ps",		"M,S,T",	0x46c0003c, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33,		0,	0 },
@@ -651,7 +651,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.le.s",		"S,T",		0x4600003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_S,	0,		I1,		0,	EE },
 {"c.le.s",		"M,S,T",	0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,		I4_32,		0,	0 },
 {"c.le.ob",		"Y,Q",		0x78000005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"c.le.ob",		"S,Q",		0x48000005, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"c.le.ob",		"S,Q",		0x48000005, 0xfc2007ff,	WR_CC|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"c.le.ps",		"S,T",		0x46c0003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"c.le.ps",		"S,T",		0x4560003e, 0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,		IL2E,		0,	0 },
 {"c.le.ps",		"M,S,T",	0x46c0003e, 0xffe000ff,	RD_S|RD_T|WR_CC|FP_D,	0,		I5_33,		0,	0 },
@@ -1092,7 +1092,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maddu1",		"d,s,t",	0x70000021, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		EE,		0,	0 },
 {"madd16",		"s,t",		0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411,		0,	0 },
 {"max.ob",		"X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"max.ob",		"D,S,Q",	0x48000007, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"max.ob",		"D,S,Q",	0x48000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"max.qh",		"X,Y,Q",	0x78200007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"max.s",		"D,S,T",	0x46000028, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	0,		EE,		0,	0 },
 {"mfbpc",		"t",		0x4000c000, 0xffe0ffff,	LCD|WR_t|RD_C0,		0,		EE,		0,	0 },
@@ -1143,7 +1143,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfcr",		"t,s",		0x70000018, 0xfc00ffff, WR_t,			0,		XLR,		0,	0 },
 {"mfsa",		"d",		0x00000028, 0xffff07ff,	WR_d,			0,		EE,		0,	0 },
 {"min.ob",		"X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"min.qh",		"X,Y,Q",	0x78200006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"min.s",		"D,S,T",	0x46000029, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,	0,		EE,		0,	0 },
 {"mov.d",		"D,S",		0x46200006, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1,		0,	SF },
@@ -1263,7 +1263,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul.d",		"D,V,T",	0x46200002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,		0,	SF },
 {"mul.s",		"D,V,T",	0x46000002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1,		0,	0 },
 {"mul.ob",		"X,Y,Q",	0x78000030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"mul.ob",		"D,S,Q",	0x48000030, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"mul.ob",		"D,S,Q",	0x48000030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"mul.ps",		"D,V,T",	0x46c00002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"mul.ps",		"D,V,T",	0x45600002, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E,		0,	0 },
 {"mul.qh",		"X,Y,Q",	0x78200030, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
@@ -1272,13 +1272,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul",			"d,v,t",	0,    (int) M_MUL,	INSN_MACRO,		0,		I1,		0,	0 },
 {"mul",			"d,v,I",	0,    (int) M_MUL_I,	INSN_MACRO,		0,		I1,		0,	0 },
 {"mula.ob",		"Y,Q",		0x78000033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1,		MX,	0 },
-{"mula.ob",		"S,Q",		0x48000033, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"mula.ob",		"S,Q",		0x48000033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mula.qh",		"Y,Q",		0x78200033, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	0,		MX,	0 },
 {"mula.s",		"S,T",		0x4600001a, 0xffe007ff,	RD_S|RD_T|FP_S,		0,		EE,		0,	0 },
 {"mulhi",		"d,s,t",	0x00000258, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5,		0,	0 },
 {"mulhiu",		"d,s,t",	0x00000259, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5,		0,	0 },
 {"mull.ob",		"Y,Q",		0x78000433, 0xfc2007ff,	RD_S|RD_T|FP_D, 	WR_MACC,	SB1,		MX,	0 },
-{"mull.ob",		"S,Q",		0x48000433, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"mull.ob",		"S,Q",		0x48000433, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mull.qh",		"Y,Q",		0x78200433, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	0,		MX,	0 },
 {"mulo",		"d,v,t",	0,    (int) M_MULO,	INSN_MACRO,		0,		I1,		0,	0 },
 {"mulo",		"d,v,I",	0,    (int) M_MULO_I,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1290,10 +1290,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulshi",		"d,s,t",	0x000002d8, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5,		0,	0 },
 {"mulshiu",		"d,s,t",	0x000002d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5,		0,	0 },
 {"muls.ob",		"Y,Q",		0x78000032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1,		MX,	0 },
-{"muls.ob",		"S,Q",		0x48000032, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"muls.ob",		"S,Q",		0x48000032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	N54,		0,	0 },
 {"muls.qh",		"Y,Q",		0x78200032, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	0,		MX,	0 },
 {"mulsl.ob",		"Y,Q",		0x78000432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1,		MX,	0 },
-{"mulsl.ob",		"S,Q",		0x48000432, 0xfc2007ff,	WR_CC|RD_S|RD_T,	0,		N54,		0,	0 },
+{"mulsl.ob",		"S,Q",		0x48000432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	N54,		0,	0 },
 {"mulsl.qh",		"Y,Q",		0x78200432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	0,		MX,	0 },
 {"mult",		"s,t",		0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1,		0,	0 },
 {"mult",		"7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              0,		D32,	0 },
@@ -1337,7 +1337,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",			"D,S,T",	0x47a00002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"nor",			"D,S,T",	0x4ba00002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"nor.ob",		"X,Y,Q",	0x7800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"nor.ob",		"D,S,Q",	0x4800000f, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"nor.ob",		"D,S,Q",	0x4800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"nor.qh",		"X,Y,Q",	0x7820000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"not",			"d,v",		0x00000027, 0xfc1f07ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },/*nor d,s,0*/
 {"or",			"d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },
@@ -1345,7 +1345,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",			"D,S,T",	0x45a00000, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"or",			"D,S,T",	0x4b20000c, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"or.ob",		"X,Y,Q",	0x7800000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"or.ob",		"D,S,Q",	0x4800000e, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"or.ob",		"D,S,Q",	0x4800000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"or.qh",		"X,Y,Q",	0x7820000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"ori",			"t,r,i",	0x34000000, 0xfc000000,	WR_t|RD_s,		0,		I1,		0,	0 },
 {"pabsdiff.ob",		"X,Y,Q",	0x78000009, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		0,	0 },
@@ -1386,10 +1386,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"phmadh",		"d,s,t",	0x70000449, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI,		0,	0 },
 {"phmsbh",		"d,s,t",	0x70000549, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO,	0,		MMI,		0,	0 },
 {"pickf.ob",		"X,Y,Q",	0x78000002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"pickf.ob",		"D,S,Q",	0x48000002, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"pickf.ob",		"D,S,Q",	0x48000002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"pickf.qh",		"X,Y,Q",	0x78200002, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"pickt.ob",		"X,Y,Q",	0x78000003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"pickt.ob",		"D,S,Q",	0x48000003, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"pickt.ob",		"D,S,Q",	0x48000003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"pickt.qh",		"X,Y,Q",	0x78200003, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"pinteh",		"d,s,t",	0x700002a9, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI,		0,	0 },
 {"pinth",		"d,s,t",	0x70000289, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		MMI,		0,	0 },
@@ -1449,13 +1449,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmacs.02",		"s,t",		0x70000092, 0xfc00ffff, MOD_HILO|RD_s|RD_t,	0,		IOCT2,		0,	0 },
 {"qmacs.03",		"s,t",		0x700000d2, 0xfc00ffff, MOD_HILO|RD_s|RD_t,	0,		IOCT2,		0,	0 },
 {"rach.ob",		"X",		0x7a00003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	SB1,		MX,	0 },
-{"rach.ob",		"D",		0x4a00003f, 0xfffff83f,	WR_D,			0,		N54,		0,	0 },
+{"rach.ob",		"D",		0x4a00003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	N54,		0,	0 },
 {"rach.qh",		"X",		0x7a20003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	0,		MX,	0 },
 {"racl.ob",		"X",		0x7800003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	SB1,		MX,	0 },
-{"racl.ob",		"D",		0x4800003f, 0xfffff83f,	WR_D,			0,		N54,		0,	0 },
+{"racl.ob",		"D",		0x4800003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	N54,		0,	0 },
 {"racl.qh",		"X",		0x7820003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	0,		MX,	0 },
 {"racm.ob",		"X",		0x7900003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	SB1,		MX,	0 },
-{"racm.ob",		"D",		0x4900003f, 0xfffff83f,	WR_D,			0,		N54,		0,	0 },
+{"racm.ob",		"D",		0x4900003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	N54,		0,	0 },
 {"racm.qh",		"X",		0x7920003f, 0xfffff83f,	WR_D|FP_D,		RD_MACC,	0,		MX,	0 },
 {"recip.d",		"D,S",		0x46200015, 0xffff003f, WR_D|RD_S|FP_D,		0,		I4_33,		0,	0 },
 {"recip.ps",		"D,S",		0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,		0,		SB1,		0,	0 },
@@ -1508,7 +1508,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"rsqrt2.s",		"D,S,T",	0x4600001f, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		0,		M3D,	0 },
 {"rzs.qh",		"X,Q",		0x78200024, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	0,		MX,	0 },
 {"rzu.ob",		"X,Q",		0x78000020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	SB1,		MX,	0 },
-{"rzu.ob",		"D,Q",		0x48000020, 0xfc20f83f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"rzu.ob",		"D,Q",		0x48000020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	N54,		0,	0 },
 {"rzu.qh",		"X,Q",		0x78200020, 0xfc20f83f,	WR_D|RD_T|FP_D,		RD_MACC,	0,		MX,	0 },
 {"saa",			"t,A(b)",	0,    (int) M_SAA_AB,	INSN_MACRO,		0,		IOCTP,		0,	0 },
 {"saa",			"t,(b)",	0x70000018, 0xfc00ffff, SM|RD_t|RD_b,		0,		IOCTP,		0,	0 },
@@ -1565,15 +1565,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sh",			"t,A(b)",	0,    (int) M_SH_AB,	INSN_MACRO,		0,		I1,		0,	0 },
 {"shfl.bfla.qh",	"X,Y,Z",	0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"shfl.mixh.ob",	"X,Y,Z",	0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"shfl.mixh.ob",	"D,S,T",	0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54,		0,	0 },
+{"shfl.mixh.ob",	"D,S,T",	0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 	0,		N54,		0,	0 },
 {"shfl.mixh.qh",	"X,Y,Z",	0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"shfl.mixl.ob",	"X,Y,Z",	0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"shfl.mixl.ob",	"D,S,T",	0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54,		0,	0 },
+{"shfl.mixl.ob",	"D,S,T",	0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 	0,		N54,		0,	0 },
 {"shfl.mixl.qh",	"X,Y,Z",	0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"shfl.pach.ob",	"X,Y,Z",	0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"shfl.pach.ob",	"D,S,T",	0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54,		0,	0 },
+{"shfl.pach.ob",	"D,S,T",	0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 	0,		N54,		0,	0 },
 {"shfl.pach.qh",	"X,Y,Z",	0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
-{"shfl.pacl.ob",	"D,S,T",	0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 	0,		N54,		0,	0 },
+{"shfl.pacl.ob",	"D,S,T",	0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 	0,		N54,		0,	0 },
 {"shfl.repa.qh",	"X,Y,Z",	0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"shfl.repb.qh",	"X,Y,Z",	0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"shfl.upsl.ob",	"X,Y,Z",	0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
@@ -1591,7 +1591,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sll",			"D,S,T",	0x45800002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"sll",			"D,S,T",	0x4b00000e, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"sll.ob",		"X,Y,Q",	0x78000010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"sll.ob",		"D,S,Q",	0x48000010, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"sll.ob",		"D,S,Q",	0x48000010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"sll.qh",		"X,Y,Q",	0x78200010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"slt",			"d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1,		0,	0 },
 {"slt",			"d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1,		0,	0 },
@@ -1626,7 +1626,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"srl",			"D,S,T",	0x45800003, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"srl",			"D,S,T",	0x4b00000f, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"srl.ob",		"X,Y,Q",	0x78000012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"srl.ob",		"D,S,Q",	0x48000012, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"srl.ob",		"D,S,Q",	0x48000012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"srl.qh",		"X,Y,Q",	0x78200012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 /* ssnop is at the start of the table.  */
 {"standby",		"",		0x42000021, 0xffffffff,	0,			0,		V1,		0,	0 },
@@ -1637,7 +1637,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub.d",		"D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1,		0,	SF },
 {"sub.s",		"D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1,		0,	0 },
 {"sub.ob",		"X,Y,Q",	0x7800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"sub.ob",		"D,S,Q",	0x4800000a, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"sub.ob",		"D,S,Q",	0x4800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"sub.ps",		"D,V,T",	0x46c00001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33|IL2F,	0,	0 },
 {"sub.ps",		"D,V,T",	0x45600001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		IL2E,		0,	0 },
 {"sub.qh",		"X,Y,Q",	0x7820000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
@@ -1756,10 +1756,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"vmm0",		"d,v,t",	0x70000010, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT,		0,	0 },
 {"vmulu",		"d,v,t",	0x7000000f, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT,		0,	0 },
 {"wach.ob",		"Y",		0x7a00003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	SB1,		MX,	0 },
-{"wach.ob",		"S",		0x4a00003e, 0xffff07ff,	RD_S,			0,		N54,		0,	0 },
+{"wach.ob",		"S",		0x4a00003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	N54,		0,	0 },
 {"wach.qh",		"Y",		0x7a20003e, 0xffff07ff,	RD_S|FP_D,		WR_MACC,	0,		MX,	0 },
 {"wacl.ob",		"Y,Z",		0x7800003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	SB1,		MX,	0 },
-{"wacl.ob",		"S,T",		0x4800003e, 0xffe007ff,	RD_S|RD_T,		0,		N54,		0,	0 },
+{"wacl.ob",		"S,T",		0x4800003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	N54,		0,	0 },
 {"wacl.qh",		"Y,Z",		0x7820003e, 0xffe007ff,	RD_S|RD_T|FP_D,		WR_MACC,	0,		MX,	0 },
 {"wait",		"",		0x42000020, 0xffffffff, NODS,   		0,		I3_32,		0,	0 },
 {"wait",		"J",		0x42000020, 0xfe00003f, NODS,   		0,		I32|N55,	0,	0 },
@@ -1771,7 +1771,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",			"D,S,T",	0x47800002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2E,		0,	0 },
 {"xor",			"D,S,T",	0x4b800002, 0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,		IL2F|IL3A,	0,	0 },
 {"xor.ob",		"X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		SB1,		MX,	0 },
-{"xor.ob",		"D,S,Q",	0x4800000d, 0xfc20003f,	WR_D|RD_S|RD_T,		0,		N54,		0,	0 },
+{"xor.ob",		"D,S,Q",	0x4800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		N54,		0,	0 },
 {"xor.qh",		"X,Y,Q",	0x7820000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		0,		MX,	0 },
 {"xori",		"t,r,i",	0x38000000, 0xfc000000,	WR_t|RD_s,		0,		I1,		0,	0 },
 {"yield",		"s",		0x7c000009, 0xfc1fffff, NODS|RD_s,		0,		0,		MT32,	0 },