aboutsummaryrefslogtreecommitdiff
path: root/opcodes
diff options
context:
space:
mode:
authorAmit Pawar <Amit.Pawar@amd.com>2016-11-28 09:21:05 -0800
committerH.J. Lu <hjl.tools@gmail.com>2016-11-28 09:21:05 -0800
commitabfcb414b9900ef996b1665323a950610dbdca43 (patch)
treed01d715e90f3c1e8e6337cc65dd3f0cdd23f63ae /opcodes
parent1a0884415891b197972f8acf59131c3c9376807f (diff)
downloadfsf-binutils-gdb-abfcb414b9900ef996b1665323a950610dbdca43.zip
fsf-binutils-gdb-abfcb414b9900ef996b1665323a950610dbdca43.tar.gz
fsf-binutils-gdb-abfcb414b9900ef996b1665323a950610dbdca43.tar.bz2
X86: Ignore REX_B bit for 32-bit XOP instructions
While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/i386-dis.c12
2 files changed, 15 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a839a68..9bfd67b 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
+ Amit Pawar <amit.pawar@amd.com>
+
+ PR binutils/20637
+ * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
+ instructions.
+
2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
* configure: Regenerate.
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 5f49f91..ada4401 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -12670,11 +12670,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info)
rex |= REX_W;
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit
- && vex.register_specifier > 0x7)
+ if (address_mode != mode_64bit)
{
- dp = &bad_opcode;
- return dp;
+ /* In 16/32-bit mode REX_B is silently ignored. */
+ rex &= ~REX_B;
+ if (vex.register_specifier > 0x7)
+ {
+ dp = &bad_opcode;
+ return dp;
+ }
}
vex.length = (*codep & 0x4) ? 256 : 128;