From abfcb414b9900ef996b1665323a950610dbdca43 Mon Sep 17 00:00:00 2001 From: Amit Pawar Date: Mon, 28 Nov 2016 09:21:05 -0800 Subject: X86: Ignore REX_B bit for 32-bit XOP instructions While decoding 32-bit XOP instructions, 64 bit registers names are printed. This patch fixes this by ignoring REX_B bit in 32-bit mode. opcodes/ PR binutils/20637 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP instructions. gas/ PR binutils/20637 * testsuite/gas/i386/xop32reg.d: New file. * testsuite/gas/i386/xop32reg.s: New file. * testsuite/gas/i386/i386.exp: Run new test. --- opcodes/ChangeLog | 7 +++++++ opcodes/i386-dis.c | 12 ++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) (limited to 'opcodes') diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a839a68..9bfd67b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,10 @@ +2016-11-28 Ramiro Polla + Amit Pawar + + PR binutils/20637 + * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP + instructions. + 2016-11-22 Ambrogino Modigliani * configure: Regenerate. diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 5f49f91..ada4401 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -12670,11 +12670,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode != mode_64bit) { - dp = &bad_opcode; - return dp; + /* In 16/32-bit mode REX_B is silently ignored. */ + rex &= ~REX_B; + if (vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } } vex.length = (*codep & 0x4) ? 256 : 128; -- cgit v1.1