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| author | Catherine Moore <clm@redhat.com> | 2010-05-26 12:59:56 +0000 |
|---|---|---|
| committer | Catherine Moore <clm@redhat.com> | 2010-05-26 12:59:56 +0000 |
| commit | f79e2745b210313ede58d9509e718f0e2506e045 (patch) | |
| tree | 1595cca36751635dd0d84bb1cfa98848de13554e /opcodes | |
| parent | f9eeb9c926526185210dd56597014ba89ee29b53 (diff) | |
| download | fsf-binutils-gdb-f79e2745b210313ede58d9509e718f0e2506e045.zip fsf-binutils-gdb-f79e2745b210313ede58d9509e718f0e2506e045.tar.gz fsf-binutils-gdb-f79e2745b210313ede58d9509e718f0e2506e045.tar.bz2 | |
gas/
* config/tc-mips.c (is_opcode_valid): Remove expansionp.
(macro_build): Change invocation of is_opcode_valid.
(mips_ip): Likewise.
gas/testsuite/
* gas/mips/mips-no-jalx.l: Delete.
* gas/mips/mips-no-jalx.s: Delete.
* gas/mips/mips-jalx-2.d: New.
* gas/mips/mips-jalx-2.s: New.
* gas/mips/mips.exp (mips-jalx-2): Run new test.
(mips-no-jalx): Remove deleted test.
include/
* opcode/mips.h (INSN_MIPS16): Remove.
opcodes/
* mips-dis.c (mips_arch): Remove INSN_MIPS16.
* mips-opc.c (I16): Remove.
(mips_builtin_op): Reclassify jalx.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 10 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 5 |
3 files changed, 12 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6725e02..29dd295 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2010-05-26 Catherine Moore <clm@codesoourcery.com> + + * mips-dis.c (mips_arch): Remove INSN_MIPS16. + * mips-opc.c (I16): Remove. + (mips_builtin_op): Reclassify jalx. + 2010-05-19 Alan Modra <amodra@gmail.com> * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 203f29f..bcfef72 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -472,13 +472,13 @@ const struct mips_arch_choice mips_arch_choices[] = MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), page 1. */ { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, - ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, + ISA_MIPS32 | INSN_SMARTMIPS, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, - (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 + (ISA_MIPS32R2 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 | INSN_MIPS3D | INSN_MT), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), @@ -486,13 +486,13 @@ const struct mips_arch_choice mips_arch_choices[] = /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, - ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, + ISA_MIPS64 | INSN_MIPS3D | INSN_MDMX, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, - (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 + (ISA_MIPS64R2 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 | INSN_DSP64 | INSN_MT | INSN_MDMX), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), @@ -524,7 +524,7 @@ const struct mips_arch_choice mips_arch_choices[] = /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ - { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, }; diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 6278a20..fafcb12 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -96,9 +96,6 @@ #define I4_33 INSN_ISA4_32R2 #define I5_33 INSN_ISA5_32R2 -/* MIPS16 ASE support. */ -#define I16 INSN_MIPS16 - /* MIPS64 MIPS-3D ASE support. */ #define M3D INSN_MIPS3D @@ -739,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] = assembler, but will never match user input (because the line above will match first). */ {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 }, -{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 }, +{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I1 }, {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 }, {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 }, {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 }, |