RISC-V: Use single h extension to control hypervisor CSRs and instructions.

According to the picture 28.1 in the current ISA spec, h is no larger the
multi-letter extension, it is a single extension after v.  Therefore, this
patch fix the implementation, and use the single h to control hypervisor
CSRs and instructions, which we promised to do before.

bfd/
    * elfxx-riscv.c (riscv_supported_std_ext): Added h with version 1.0 after v.
    (riscv_supported_std_h_ext): Removed.
    (riscv_all_supported_ext): Updated since riscv_supported_std_h_ext is removed.
    (riscv_prefix_ext_class): Removed RV_ISA_CLASS_H.
    (parse_config): Updated since riscv_prefix_ext_class is removed.
    (riscv_recognized_prefixed_ext): Likewise.
    (riscv_get_default_ext_version): Likewise.
    (riscv_multi_subset_supports): Handle INSN_CLASS_H for hypervisor instructions.
    (riscv_multi_subset_supports_ext): Likewise.
gas/
    * config/tc-riscv.c (riscv_csr_class): Added CSR_CLASS_H and CSR_CLASS_H_32 for
    hypervisor CSRs.
    (riscv_csr_address): Likewise.
    * testsuite/gas/riscv/csr-version-1p10.d: Updated since hypervisor CSRs are
    controlled by single h extension for now.
    * testsuite/gas/riscv/csr-version-1p10.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p11.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p11.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p12.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p12.l: Likewise.
    * testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
    * testsuite/gas/riscv/csr-version-1p9p1.l: Likewise.
    * testsuite/gas/riscv/h-ext-32.d: Added h to architecture string.
    * testsuite/gas/riscv/h-ext-64.d: Likewise.
    * testsuite/gas/riscv/march-fail-single-prefix-h: Removed since h is no
    longer multi-letter extension.
    * testsuite/gas/riscv/march-fail-unknown-h.d: Likewise.
include/
    * opcode/riscv-opc.h: Control hypervisor CSRs by h extension, rather than
    the privileged spec verisons.
    * opcode/riscv.h (riscv_insn_class): Added INSN_CLASS_H.
opcodes/
    * riscv-opc.c (riscv_opcodes): Control hypervisor instructions by h extension.

1 files changed, 19 insertions, 19 deletions

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 6355f80..d5cedbe 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1805,25 +1805,25 @@ const struct riscv_opcode riscv_opcodes[] =
 {"hinval.gvma",     0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 },
 
 /* Hypervisor instructions.  */
-{"hfence.vvma", 0, INSN_CLASS_I, "",       MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
-{"hfence.vvma", 0, INSN_CLASS_I, "s",      MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS },
-{"hfence.vvma", 0, INSN_CLASS_I, "s,t",    MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
-{"hfence.gvma", 0, INSN_CLASS_I, "",       MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
-{"hfence.gvma", 0, INSN_CLASS_I, "s",      MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, INSN_ALIAS },
-{"hfence.gvma", 0, INSN_CLASS_I, "s,t",    MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },
-{"hlv.b",       0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_B, MASK_HLV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"hlv.bu",      0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_BU, MASK_HLV_BU, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"hlv.h",       0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_H, MASK_HLV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"hlv.hu",      0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_HU, MASK_HLV_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"hlvx.hu",     0, INSN_CLASS_I, "d,0(s)", MATCH_HLVX_HU, MASK_HLVX_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"hlv.w",       0, INSN_CLASS_I, "d,0(s)", MATCH_HLV_W, MASK_HLV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"hlv.wu",     64, INSN_CLASS_I, "d,0(s)", MATCH_HLV_WU, MASK_HLV_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"hlvx.wu",     0, INSN_CLASS_I, "d,0(s)", MATCH_HLVX_WU, MASK_HLVX_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"hlv.d",      64, INSN_CLASS_I, "d,0(s)", MATCH_HLV_D, MASK_HLV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
-{"hsv.b",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_B, MASK_HSV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
-{"hsv.h",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_H, MASK_HSV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"hsv.w",       0, INSN_CLASS_I, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
-{"hsv.d",      64, INSN_CLASS_I, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"hfence.vvma", 0, INSN_CLASS_H, "",       MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.vvma", 0, INSN_CLASS_H, "s",      MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.vvma", 0, INSN_CLASS_H, "s,t",    MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA, match_opcode, 0 },
+{"hfence.gvma", 0, INSN_CLASS_H, "",       MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.gvma", 0, INSN_CLASS_H, "s",      MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA|MASK_RS2, match_opcode, INSN_ALIAS },
+{"hfence.gvma", 0, INSN_CLASS_H, "s,t",    MATCH_HFENCE_GVMA, MASK_HFENCE_GVMA, match_opcode, 0 },
+{"hlv.b",       0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_B, MASK_HLV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hlv.bu",      0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_BU, MASK_HLV_BU, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hlv.h",       0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_H, MASK_HLV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlv.hu",      0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_HU, MASK_HLV_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlvx.hu",     0, INSN_CLASS_H, "d,0(s)", MATCH_HLVX_HU, MASK_HLVX_HU, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hlv.w",       0, INSN_CLASS_H, "d,0(s)", MATCH_HLV_W, MASK_HLV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlv.wu",     64, INSN_CLASS_H, "d,0(s)", MATCH_HLV_WU, MASK_HLV_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlvx.wu",     0, INSN_CLASS_H, "d,0(s)", MATCH_HLVX_WU, MASK_HLVX_WU, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hlv.d",      64, INSN_CLASS_H, "d,0(s)", MATCH_HLV_D, MASK_HLV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
+{"hsv.b",       0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_B, MASK_HSV_B, match_opcode, INSN_DREF|INSN_1_BYTE },
+{"hsv.h",       0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_H, MASK_HSV_H, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"hsv.w",       0, INSN_CLASS_H, "t,0(s)", MATCH_HSV_W, MASK_HSV_W, match_opcode, INSN_DREF|INSN_4_BYTE },
+{"hsv.d",      64, INSN_CLASS_H, "t,0(s)", MATCH_HSV_D, MASK_HSV_D, match_opcode, INSN_DREF|INSN_8_BYTE },
 
 /* Terminate the list.  */
 {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}