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| author | H.J. Lu <hjl.tools@gmail.com> | 2017-06-21 08:30:01 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2017-06-21 08:30:52 -0700 |
| commit | c2f7640243bdab93cafb3bf516e17a72fcc2f051 (patch) | |
| tree | 7fc98157f0278037b2bea8705e8ae8c3120fa39c /opcodes | |
| parent | 9fef80d683d79934bacd3221f5252ce8c14ff5c0 (diff) | |
| download | fsf-binutils-gdb-c2f7640243bdab93cafb3bf516e17a72fcc2f051.zip fsf-binutils-gdb-c2f7640243bdab93cafb3bf516e17a72fcc2f051.tar.gz fsf-binutils-gdb-c2f7640243bdab93cafb3bf516e17a72fcc2f051.tar.bz2 | |
x86: CET v2.0: Rename savessp to saveprevssp
Replace savessp with saveprevssp for CET v2.0:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
gas/
* testsuite/gas/i386/cet-intel.d: Updated.
* testsuite/gas/i386/cet.d: Likewise.
* testsuite/gas/i386/x86-64-cet-intel.d: Likewise.
* testsuite/gas/i386/x86-64-cet.d: Likewise.
* testsuite/gas/i386/cet.s: Replace savessp with saveprevssp.
* testsuite/gas/i386/x86-64-cet.s: Likewise.
opcodes/
* i386-dis.c (prefix_table): Replace savessp with saveprevssp.
* i386-opc.tbl: Likewise.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/i386-dis.c | 2 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 2 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 2 |
4 files changed, 9 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 671837f..3ffafa1 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> + * i386-dis.c (prefix_table): Replace savessp with saveprevssp. + * i386-opc.tbl: Likewise. + * i386-tbl.h: Regenerated. + +2017-06-21 H.J. Lu <hongjiu.lu@intel.com> + * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" and "jmp{&|}". (NOTRACK_Fixup): Support memory indirect branch with NOTRACK diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 2e35e38..58d4c06 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -3798,7 +3798,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ { { Bad_Opcode }, - { "savessp", { Skip_MODRM }, PREFIX_OPCODE }, + { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, }, /* PREFIX_0F10 */ diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5b1a4fd..47e1f66 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -6013,7 +6013,7 @@ incsspd, 0, 0xf30f01e9, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s incsspq, 0, 0xf30f01e9, None, 3, CpuCET|Cpu64, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { 0 } rdsspd, 1, 0xf30f1e, 0x1, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32 } rdsspq, 1, 0xf30f1e, 0x1, 2, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64 } -savessp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } +saveprevssp, 0, 0xf30f01ea, None, 3, CpuCET, IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 } rstorssp, 1, 0xf30f01, 0x5, 2, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } wrssd, 2, 0x0f38f6, None, 3, CpuCET, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } wrssq, 2, 0x0f38f6, None, 3, CpuCET|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Reg64, Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index 1fcd003..4bc3878 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -92045,7 +92045,7 @@ const insn_template i386_optab[] = { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, - { "savessp", 0, 0xf30f01ea, None, 3, + { "saveprevssp", 0, 0xf30f01ea, None, 3, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |