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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 11:02:28 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | a97330e723cf3c639a951329ac5fe2797528249b (patch) | |
| tree | 9085698ab114327b7807d6763fead55c0f4b8d6e /opcodes | |
| parent | ff6054520cc86ac2f34c21bcc2e44ede50b56cdc (diff) | |
| download | fsf-binutils-gdb-a97330e723cf3c639a951329ac5fe2797528249b.zip fsf-binutils-gdb-a97330e723cf3c639a951329ac5fe2797528249b.tar.gz fsf-binutils-gdb-a97330e723cf3c639a951329ac5fe2797528249b.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 20 |
2 files changed, 26 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 15c1bac..776aa0f 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * aarch64-opc.c (aarch64_sys_regs): New entries for + scxtnum_el[0,1,2,3,12] and id_pfr2_el1. + (aarch64_sys_reg_supported_p): New checks for above. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New. (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag with the hint immediate. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index d2a4f2f..4cf39d2 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3733,6 +3733,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */ { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */ { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */ + { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */ { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */ { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */ { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */ @@ -3869,6 +3870,11 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 }, { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 }, { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 }, + { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT }, + { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT }, + { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT }, + { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT }, + { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT }, { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */ { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */ { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */ @@ -4108,6 +4114,20 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN)) return FALSE; + /* SCXTNUM_ELx registers. */ + if ((reg->value == CPENC (3, 3, C13, C0, 7) + || reg->value == CPENC (3, 0, C13, C0, 7) + || reg->value == CPENC (3, 4, C13, C0, 7) + || reg->value == CPENC (3, 6, C13, C0, 7) + || reg->value == CPENC (3, 5, C13, C0, 7)) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM)) + return FALSE; + + /* ID_PFR2_EL1 register. */ + if (reg->value == CPENC(3, 0, C0, C3, 4) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2)) + return FALSE; + /* Virtualization host extensions: system registers. */ if ((reg->value == CPENC (3, 4, C2, C0, 1) || reg->value == CPENC (3, 4, C13, C0, 1) |