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| author | Jan Beulich <jbeulich@suse.com> | 2022-11-24 09:35:17 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-11-24 09:35:17 +0100 |
| commit | a122baf523b0d03c43abeaa797b82d51aac91061 (patch) | |
| tree | 8f67c1a61b0982f80d9513b3d4ecf1968472df0f /opcodes | |
| parent | c9f5b96bdab031e9520d98e01ee1bef1ffd3b961 (diff) | |
| download | fsf-binutils-gdb-a122baf523b0d03c43abeaa797b82d51aac91061.zip fsf-binutils-gdb-a122baf523b0d03c43abeaa797b82d51aac91061.tar.gz fsf-binutils-gdb-a122baf523b0d03c43abeaa797b82d51aac91061.tar.bz2 | |
x86: add missing CheckRegSize
To properly and predictably determine operand size encoding (operand
size or REX.W prefixes), consistent operand sizes need to be specified.
Add CheckRegSize where this was previously missing.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/i386-opc.tbl | 6 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 6 |
2 files changed, 6 insertions, 6 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 82011c9..4673075 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -928,11 +928,11 @@ ud2, 0xf0b, None, Cpu186, NoSuf, {} // alias for ud2 ud2a, 0xf0b, None, Cpu186, NoSuf, {} // 2nd. official undefined instr. -ud1, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud1, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // alias for ud1 -ud2b, 0xfb9, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud2b, 0xfb9, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } // 3rd official undefined instr (older CPUs don't take a ModR/M byte) -ud0, 0xfff, None, Cpu186, Modrm|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } +ud0, 0xfff, None, Cpu186, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } cmov<cc>, 0xf4<cc:opc>, None, CpuCMOV, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex, Reg16|Reg32|Reg64 } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index a9bc696..3830e22 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -9021,7 +9021,7 @@ const insn_template i386_optab[] = { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } } } }, { "ud1", 0xb9, 2, None, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9036,7 +9036,7 @@ const insn_template i386_optab[] = { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { "ud2b", 0xb9, 2, None, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -9051,7 +9051,7 @@ const insn_template i386_optab[] = { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0 } } } }, { "ud0", 0xff, 2, None, - { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, + { 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |