diff options
author | Peter Bergner <bergner@vnet.ibm.com> | 2008-08-02 04:38:51 +0000 |
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committer | Peter Bergner <bergner@vnet.ibm.com> | 2008-08-02 04:38:51 +0000 |
commit | 9b4e57660d385d9135549aeb8360ebfa14fb3990 (patch) | |
tree | e508e99bbab020f78ccd3b320ca8bf30b1b95b96 /opcodes | |
parent | dbe454a3b5f62a101aa4a8b290a7c63a40f8ac52 (diff) | |
download | fsf-binutils-gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.zip fsf-binutils-gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.tar.gz fsf-binutils-gdb-9b4e57660d385d9135549aeb8360ebfa14fb3990.tar.bz2 |
gas/
* config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags.
Handle -mvsx and -mpower7.
(md_show_usage): Document -mpower7 and -mvsx.
* doc/as.texinfo (Target PowerPC): Document -mvsx.
* doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7.
gas/testsuite/
* gas/ppc/power7.d: New.
* gas/ppc/power7.s: Likewise.
* gas/ppc/ppc.exp: Run power7 test.
include/opcode/
* ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
opcodes/
* ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
(print_insn_powerpc): Prepend 'vs' when printing VSX registers.
(print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
* ppc-opc.c (insert_xt6): New static function.
(extract_xt6): Likewise.
(insert_xa6): Likewise.
(extract_xa6: Likewise.
(insert_xb6): Likewise.
(extract_xb6): Likewise.
(insert_xb6s): Likewise.
(extract_xb6s): Likewise.
(XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
XX3DM_MASK, PPCVSX): New.
(powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
"stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 18 | ||||
-rw-r--r-- | opcodes/ppc-dis.c | 16 | ||||
-rw-r--r-- | opcodes/ppc-opc.c | 144 |
3 files changed, 177 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1560fa9..4f5b607 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,21 @@ +2008-08-01 Peter Bergner <bergner@vnet.ibm.com> + + * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. + (print_insn_powerpc): Prepend 'vs' when printing VSX registers. + (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. + * ppc-opc.c (insert_xt6): New static function. + (extract_xt6): Likewise. + (insert_xa6): Likewise. + (extract_xa6: Likewise. + (insert_xb6): Likewise. + (extract_xb6): Likewise. + (insert_xb6s): Likewise. + (extract_xb6s): Likewise. + (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, + XX3DM_MASK, PPCVSX): New. + (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", + "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp". + 2008-08-01 Pedro Alves <pedro@codesourcery.com> * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. diff --git a/opcodes/ppc-dis.c b/opcodes/ppc-dis.c index 7d4f9e1..bde4c49 100644 --- a/opcodes/ppc-dis.c +++ b/opcodes/ppc-dis.c @@ -107,7 +107,17 @@ powerpc_init_dialect (struct disassemble_info *info) if (info->disassembler_options && strstr (info->disassembler_options, "power6") != NULL) - dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 | PPC_OPCODE_ALTIVEC; + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_ALTIVEC; + + if (info->disassembler_options + && strstr (info->disassembler_options, "power7") != NULL) + dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5 | PPC_OPCODE_POWER6 + | PPC_OPCODE_ALTIVEC | PPC_OPCODE_VSX; + + if (info->disassembler_options + && strstr (info->disassembler_options, "vsx") != NULL) + dialect |= PPC_OPCODE_VSX; if (info->disassembler_options && strstr (info->disassembler_options, "any") != NULL) @@ -321,6 +331,8 @@ print_insn_powerpc (bfd_vma memaddr, (*info->fprintf_func) (info->stream, "f%ld", value); else if ((operand->flags & PPC_OPERAND_VR) != 0) (*info->fprintf_func) (info->stream, "v%ld", value); + else if ((operand->flags & PPC_OPERAND_VSR) != 0) + (*info->fprintf_func) (info->stream, "vs%ld", value); else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0) (*info->print_address_func) (memaddr + value, info); else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) @@ -401,6 +413,8 @@ the -M switch:\n"); fprintf (stream, " power4 Disassemble the Power4 instructions\n"); fprintf (stream, " power5 Disassemble the Power5 instructions\n"); fprintf (stream, " power6 Disassemble the Power6 instructions\n"); + fprintf (stream, " power7 Disassemble the Power7 instructions\n"); + fprintf (stream, " vsx Disassemble the Vector-Scalar (VSX) instructions\n"); fprintf (stream, " 32 Do not disassemble 64-bit instructions\n"); fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n"); } diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 617d976..e0d833c 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -73,6 +73,14 @@ static unsigned long insert_sprg (unsigned long, long, ppc_cpu_t, const char **) static long extract_sprg (unsigned long, ppc_cpu_t, int *); static unsigned long insert_tbr (unsigned long, long, ppc_cpu_t, const char **); static long extract_tbr (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xt6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xt6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xa6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xa6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xb6 (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xb6 (unsigned long, ppc_cpu_t, int *); +static unsigned long insert_xb6s (unsigned long, long, ppc_cpu_t, const char **); +static long extract_xb6s (unsigned long, ppc_cpu_t, int *); /* The operands table. @@ -600,6 +608,28 @@ const struct powerpc_operand powerpc_operands[] = #define URC URB + 1 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, + /* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ +#define XS6 URC + 1 +#define XT6 XS6 + { 0x3f, -1, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, + + /* The XA field in an XX3 form instruction. This is split. */ +#define XA6 XT6 + 1 + { 0x3f, -1, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, + + /* The XB field in an XX3 form instruction. This is split. */ +#define XB6 XA6 + 1 + { 0x3f, -1, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, + + /* The XB field in an XX3 form instruction when it must be the same as + the XA field in the instruction. This is used in extended mnemonics + like xvmovdp. This is split. */ +#define XB6S XB6 + 1 + { 0x3f, -1, insert_xb6s, extract_xb6s, PPC_OPERAND_FAKE }, + + /* The DM field in an XX3 form instruction. */ +#define DM XB6S + 1 + { 0x3, 8, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -1292,6 +1322,89 @@ extract_tbr (unsigned long insn, ret = 0; return ret; } + +/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ + +static unsigned long +insert_xt6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); +} + +static long +extract_xt6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); +} + +/* The XA field in an XX3 form instruction. This is split. */ + +static unsigned long +insert_xa6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); +} + +static long +extract_xa6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); +} + +/* The XB field in an XX3 form instruction. This is split. */ + +static unsigned long +insert_xb6 (unsigned long insn, + long value, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); +} + +static long +extract_xb6 (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); +} + +/* The XB field in an XX3 form instruction when it must be the same as + the XA field in the instruction. This is used for extended + mnemonics like xvmovdp. This operand is marked FAKE. The insertion + function just copies the XA field into the XB field, and the + extraction function just checks that the fields are the same. */ + +static unsigned long +insert_xb6s (unsigned long insn, + long value ATTRIBUTE_UNUSED, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) +{ + return insn | (((insn >> 16) & 0x1f) << 11) | (((insn >> 2) & 0x1) << 1); +} + +static long +extract_xb6s (unsigned long insn, + ppc_cpu_t dialect ATTRIBUTE_UNUSED, + int *invalid) +{ + if ((((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + || (((insn >> 2) & 0x1) != ((insn >> 1) & 0x1))) + *invalid = 1; + return 0; +} /* Macros used to form opcodes. */ @@ -1437,6 +1550,12 @@ extract_tbr (unsigned long insn, /* An X form instruction. */ #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) +/* An XX3 form instruction. */ +#define XX3(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0xff) << 3)) + +#define XX3DM(op, xop, dm) (XX3 (op, ((unsigned long)(xop) & 0x1f)) \ + | ((((unsigned long)(dm)) & 0x3) << 8)) + /* A Z form instruction. */ #define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) @@ -1449,6 +1568,15 @@ extract_tbr (unsigned long insn, /* The mask for an X form instruction. */ #define X_MASK XRC (0x3f, 0x3ff, 1) +/* The mask for an XX1 form instruction. */ +#define XX1_MASK X (0x3f, 0x3ff) + +/* The mask for an XX3 form instruction. */ +#define XX3_MASK XX3 (0x3f, 0xff) + +/* The mask for an XX3 form instruction with the DM bits specified. */ +#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) + /* The mask for a Z form instruction. */ #define Z_MASK ZRC (0x3f, 0x1ff, 1) #define Z2_MASK ZRC (0x3f, 0xff, 1) @@ -1701,6 +1829,7 @@ extract_tbr (unsigned long insn, #define PPC860 PPC #define PPCPS PPC_OPCODE_PPCPS #define PPCVEC PPC_OPCODE_ALTIVEC +#define PPCVSX PPC_OPCODE_VSX #define POWER PPC_OPCODE_POWER #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 @@ -4441,6 +4570,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divo.", XO(31,331,1,1), XO_MASK, M601, {RT, RA, RB}}, {"lduxe", X(31,831), X_MASK, BOOKE64, {RT, RA0, RB}}, +{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, {XT6, RA, RB}}, + {"slbmfev", X(31,851), XRA_MASK, PPC64, {RT, RB}}, {"lbzcix", X(31,853), X_MASK, POWER6, {RT, RA0, RB}}, @@ -4456,6 +4587,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divso", XO(31,363,1,0), XO_MASK, M601, {RT, RA, RB}}, {"divso.", XO(31,363,1,1), XO_MASK, M601, {RT, RA, RB}}, +{"lxvd2ux", X(31,876), XX1_MASK, PPCVSX, {XT6, RA, RB}}, + {"ldcix", X(31,885), X_MASK, POWER6, {RT, RA0, RB}}, {"stvlxl", X(31,903), X_MASK, CELL, {VS, RA0, RB}}, @@ -4526,6 +4659,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwuo", XO(31,459,1,0), XO_MASK, PPC, {RT, RA, RB}}, {"divwuo.", XO(31,459,1,1), XO_MASK, PPC, {RT, RA, RB}}, +{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, {XS6, RA, RB}}, + {"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, {RT, RA}}, {"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, {RT, RA}}, {"tlbwe", X(31,978), X_MASK, PPC403|BOOKE, {RSO, RAOPT, SHO}}, @@ -4559,6 +4694,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"divwo", XO(31,491,1,0), XO_MASK, PPC, {RT, RA, RB}}, {"divwo.", XO(31,491,1,1), XO_MASK, PPC, {RT, RA, RB}}, +{"stxvd2ux", X(31,1004), XX1_MASK, PPCVSX, {XS6, RA, RB}}, + {"tlbli", X(31,1010), XRTRA_MASK, PPC, {RB}}, {"stdcix", X(31,1013), X_MASK, POWER6, {RS, RA0, RB}}, @@ -4770,6 +4907,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stfq", OP(60), OP_MASK, POWER2, {FRS, D, RA}}, {"psq_st", OP(60), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, + +{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, +{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, +{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, {XT6, XA6, XB6, DM}}, +{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6S}}, +{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, {XT6, XA6, XB6}}, + {"psq_stu", OP(61), OP_MASK, PPCPS, {FRS,PSD,RA,PSW,PSQ}}, {"stfqu", OP(61), OP_MASK, POWER2, {FRS, D, RA}}, |