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authorNick Clifton <nickc@redhat.com>2013-08-23 07:54:19 +0000
committerNick Clifton <nickc@redhat.com>2013-08-23 07:54:19 +0000
commit9aff4b7ac12edba0c170c2a55763c3973b708749 (patch)
tree6b2fb65592c8172b25dd9b405d68747295266e79 /opcodes
parent865acd35866cc017ec11e48fbacc8d57d3943361 (diff)
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PR binutils/15834
Fix typos: --- bfd/bfdio.c | 2 +- bfd/elf32-spu.c | 2 +- bfd/elfnn-aarch64.c | 2 +- binutils/od-xcoff.c | 2 +- config/tcl.m4 | 2 +- gas/config/tc-ia64.c | 2 +- gas/config/tc-sparc.c | 2 +- gas/config/tc-z80.c | 12 ++++++------ gas/doc/c-i386.texi | 6 +++--- gas/doc/c-m32r.texi | 2 +- gas/testsuite/gas/d10v/instruction_packing.d | 2 +- gas/testsuite/gas/z80/atend.d | 2 +- gold/object.h | 2 +- include/gdb/remote-sim.h | 2 +- include/opcode/ChangeLog | 2 +- include/opcode/i960.h | 2 +- ld/testsuite/ld-mips-elf/mips16-pic-1.inc | 2 +- opcodes/aarch64-asm.c | 2 +- opcodes/aarch64-dis.c | 2 +- opcodes/msp430-dis.c | 2 +-
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog7
-rw-r--r--opcodes/aarch64-asm.c4
-rw-r--r--opcodes/aarch64-dis.c4
-rw-r--r--opcodes/msp430-dis.c2
4 files changed, 12 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index af6ba2b..7427f14 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
+
+ PR binutils/15834
+ * aarch64-asm.c: Fix typos.
+ * aarch64-dis.c: Likewise.
+ * msp430-dis.c: Likewise.
+
2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 96396e8..27a4def 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1,5 +1,5 @@
/* aarch64-asm.c -- AArch64 assembler support.
- Copyright 2012, 2013 Free Software Foundation, Inc.
+ Copyright 2012-2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
@@ -31,7 +31,7 @@
N.B. the fields are required to be in such an order than the least signficant
field for VALUE comes the first, e.g. the <index> in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
- is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+ is encoded in H:L:M in some cases, the fields H:L:M should be passed in
the order of M, L, H. */
static inline void
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index c757316..c403be8 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1,5 +1,5 @@
/* aarch64-dis.c -- AArch64 disassembler.
- Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
+ Copyright 2009-2013 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
@@ -120,7 +120,7 @@ parse_aarch64_dis_options (const char *options)
N.B. the fields are required to be in such an order than the most signficant
field for VALUE comes the first, e.g. the <index> in
SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
- is encoded in H:L:M in some cases, the the fields H:L:M should be passed in
+ is encoded in H:L:M in some cases, the fields H:L:M should be passed in
the order of H, L, M. */
static inline aarch64_insn
diff --git a/opcodes/msp430-dis.c b/opcodes/msp430-dis.c
index 46da3cc..c314638 100644
--- a/opcodes/msp430-dis.c
+++ b/opcodes/msp430-dis.c
@@ -836,7 +836,7 @@ msp430x_calla_instr (disassemble_info * info,
break;
default:
- strcpy (comm1, _("unercognised CALLA addressing mode"));
+ strcpy (comm1, _("unrecognised CALLA addressing mode"));
return -1;
}