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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2018-01-09 14:15:00 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2018-01-09 14:21:59 +0000 |
| commit | 91d8b670661883fc0472fd05cf0e54d0e357c187 (patch) | |
| tree | b5301faacc52bb5d5c67e2e99f31ba20052e5898 /opcodes | |
| parent | be2e7d95414eb78f29312f30e62d4cabd55f9fda (diff) | |
| download | fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.zip fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.tar.gz fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.tar.bz2 | |
[Arm] Add CSDB instruction
CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.
OK? If so, please commit on my behalf as I don't have commit rights
over here.
Thanks, James
---
opcodes/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
gas/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 585169f..96bc41c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> + * arm-dis.c (arm_opcodes): Add csdb. + (thumb32_opcodes): Add csdb. + +2018-01-09 James Greenhalgh <james.greenhalgh@arm.com> + * aarch64-tbl.h (aarch64_opcode_table): Add "csdb". * aarch64-asm-2.c: Regenerate. * aarch64-dis-2.c: Regenerate. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index db48b32..5efe031 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1901,6 +1901,9 @@ static const struct opcode32 arm_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"}, + /* CSDB. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V3), 0xe320f014, 0xffffffff, "csdb"}, + /* ARM V6K NOP hints. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0x0320f001, 0x0fffffff, "yield%c"}, @@ -2819,6 +2822,9 @@ static const struct opcode32 thumb32_opcodes[] = /* Security extension instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_SEC), 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, + /* CSDB. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8014, 0xffffffff, "csdb"}, + /* Instructions defined in the basic V6T2 set. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8000, 0xffffffff, "nop%c.w"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8001, 0xffffffff, "yield%c.w"}, |