[ARC] Improve printing of pc-relative instructions.

opcodes/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
	* arc-opc.c (SIMM21_A16_5): Make it pc-relative.

gas/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/gas/arc/b.d : Update test.
	* testsuite/gas/arc/bl.d: Likewise.
	* testsuite/gas/arc/jli-1.d: Likewise.
	* testsuite/gas/arc/lp.d: Likewise.
	* testsuite/gas/arc/pcl-relocs.d: Likewise.
	* testsuite/gas/arc/pcrel-relocs.d: Likewise.
	* testsuite/gas/arc/pic-relocs.d: Likewise.
	* testsuite/gas/arc/plt-relocs.d: Likewise.
	* testsuite/gas/arc/pseudos.d: Likewise.
	* testsuite/gas/arc/relax-avoid2.d: Likewise.
	* testsuite/gas/arc/relax-avoid3.d: Likewise.
	* testsuite/gas/arc/relax-b.d: Likewise.
	* testsuite/gas/arc/tls-relocs.d: Likewise.
	* testsuite/gas/arc/relax-add01.d: Likewise.
	* testsuite/gas/arc/relax-add04.d: Likewise.
	* testsuite/gas/arc/relax-ld01.d: Likewise.
	* testsuite/gas/arc/relax-sub01.d: Likewise.
	* testsuite/gas/arc/relax-sub02.d: Likewise.
	* testsuite/gas/arc/relax-sub04.d: Likewise.
	* testsuite/gas/arc/pcl-print.s: New file.
	* testsuite/gas/arc/pcl-print.d: Likewise.
	* testsuite/gas/arc/nps400-12.d: Likewise.

ld/
2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>

	* testsuite/ld-arc/jli-simple.d: Update test.

3 files changed, 52 insertions, 17 deletions

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 84eaa6f..1d835c9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2017-11-21  Claudiu Zissulescu <claziss@synopsys.com>
+
+	* arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
+	* arc-opc.c (SIMM21_A16_5): Make it pc-relative.
+
 2017-11-16  Tamar Christina  <tamar.christina@arm.com>
 
 	* aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c
index 7541b74..71acc10 100644
--- a/opcodes/arc-dis.c
+++ b/opcodes/arc-dis.c
@@ -923,9 +923,10 @@ print_insn_arc (bfd_vma memaddr,
   bfd_boolean open_braket;
   int size;
   const struct arc_operand *operand;
-  int value;
+  int value, vpcl;
   struct arc_operand_iterator iter;
   struct arc_disassemble_info *arc_infop;
+  bfd_boolean rpcl = FALSE, rset = FALSE;
 
   if (info->disassembler_options)
     {
@@ -1022,6 +1023,7 @@ print_insn_arc (bfd_vma memaddr,
 
   /* Read the insn into a host word.  */
   status = (*info->read_memory_func) (memaddr, buffer, size, info);
+
   if (status != 0)
     {
       (*info->memory_error_func) (status, memaddr, info);
@@ -1132,23 +1134,23 @@ print_insn_arc (bfd_vma memaddr,
       switch (insn_len)
 	{
 	case 2:
-	  (*info->fprintf_func) (info->stream, ".long %#04llx",
+	  (*info->fprintf_func) (info->stream, ".shor\t%#04llx",
 				 insn & 0xffff);
 	  break;
 	case 4:
-	  (*info->fprintf_func) (info->stream, ".long %#08llx",
+	  (*info->fprintf_func) (info->stream, ".word\t%#08llx",
 				 insn & 0xffffffff);
 	  break;
 	case 6:
-	  (*info->fprintf_func) (info->stream, ".long %#08llx",
+	  (*info->fprintf_func) (info->stream, ".long\t%#08llx",
 				 insn & 0xffffffff);
-	  (*info->fprintf_func) (info->stream, ".long %#04llx",
+	  (*info->fprintf_func) (info->stream, ".long\t%#04llx",
 				 (insn >> 32) & 0xffff);
 	  break;
 	case 8:
-	  (*info->fprintf_func) (info->stream, ".long %#08llx",
+	  (*info->fprintf_func) (info->stream, ".long\t%#08llx",
 				 insn & 0xffffffff);
-	  (*info->fprintf_func) (info->stream, ".long %#08llx",
+	  (*info->fprintf_func) (info->stream, ".long\t%#08llx",
 				 insn >> 32);
 	  break;
 	default:
@@ -1178,6 +1180,7 @@ print_insn_arc (bfd_vma memaddr,
 
   /* Now extract and print the operands.  */
   operand = NULL;
+  vpcl = 0;
   while (operand_iterator_next (&iter, &operand, &value))
     {
       if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
@@ -1215,6 +1218,20 @@ print_insn_arc (bfd_vma memaddr,
 
       need_comma = TRUE;
 
+      if (operand->flags & ARC_OPERAND_PCREL)
+	{
+	  rpcl = TRUE;
+	  vpcl = value;
+	  rset = TRUE;
+
+	  info->target = (bfd_vma) (memaddr & ~3) + value;
+	}
+      else if (!(operand->flags & ARC_OPERAND_IR))
+	{
+	  vpcl = value;
+	  rset = TRUE;
+	}
+
       /* Print the operand as directed by the flags.  */
       if (operand->flags & ARC_OPERAND_IR)
 	{
@@ -1232,6 +1249,10 @@ print_insn_arc (bfd_vma memaddr,
 		rname = regnames[value + 1];
 	      (*info->fprintf_func) (info->stream, "%s", rname);
 	    }
+	  if (value == 63)
+	    rpcl = TRUE;
+	  else
+	    rpcl = FALSE;
 	}
       else if (operand->flags & ARC_OPERAND_LIMM)
 	{
@@ -1247,15 +1268,6 @@ print_insn_arc (bfd_vma memaddr,
 		info->target = (bfd_vma) value;
 	    }
 	}
-      else if (operand->flags & ARC_OPERAND_PCREL)
-	{
-	   /* PCL relative.  */
-	  if (info->flags & INSN_HAS_RELOC)
-	    memaddr = 0;
-	  (*info->print_address_func) ((memaddr & ~3) + value, info);
-
-	  info->target = (bfd_vma) (memaddr & ~3) + value;
-	}
       else if (operand->flags & ARC_OPERAND_SIGNED)
 	{
 	  const char *rname = get_auxreg (opcode, value, isa_mask);
@@ -1283,6 +1295,7 @@ print_insn_arc (bfd_vma memaddr,
 	      && !(operand->flags & ARC_OPERAND_ALIGNED16)
 	      && value >= 0 && value <= 14)
 	    {
+	      /* Leave/Enter mnemonics.  */
 	      switch (value)
 		{
 		case 0:
@@ -1296,6 +1309,8 @@ print_insn_arc (bfd_vma memaddr,
 					 regnames[13 + value - 1]);
 		  break;
 		}
+	      rpcl = FALSE;
+	      rset = FALSE;
 	    }
 	  else
 	    {
@@ -1326,6 +1341,21 @@ print_insn_arc (bfd_vma memaddr,
       arc_infop->operands_count ++;
     }
 
+  /* Pretty print extra info for pc-relative operands.  */
+  if (rpcl && rset)
+    {
+      if (info->flags & INSN_HAS_RELOC)
+	/* If the instruction has a reloc associated with it, then the
+	   offset field in the instruction will actually be the addend
+	   for the reloc.  (We are using REL type relocs).  In such
+	   cases, we can ignore the pc when computing addresses, since
+	   the addend is not currently pc-relative.  */
+	memaddr = 0;
+
+      (*info->fprintf_func) (info->stream, "\t;");
+      (*info->print_address_func) ((memaddr & ~3) + vpcl, info);
+    }
+
   return insn_len;
 }
 
diff --git a/opcodes/arc-opc.c b/opcodes/arc-opc.c
index e57877e..56c9aaf 100644
--- a/opcodes/arc-opc.c
+++ b/opcodes/arc-opc.c
@@ -2006,7 +2006,7 @@ const struct arc_operand arc_operands[] =
   /* SIMM21_A16_5 mask = 00000111111111102222222222000000.  */
 #define SIMM21_A16_5	   (UIMM6_8 + 1)
   {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
-   | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
+   | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
    insert_simm21_a16_5, extract_simm21_a16_5},
 
   /* SIMM25_A16_5 mask = 00000111111111102222222222003333.  */