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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2015-08-13 11:39:08 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2015-08-13 11:39:08 +0100 |
| commit | 4ab90a7a90ccf8a671f139c1c6387ba8028e6011 (patch) | |
| tree | bc942f5897d56e9d41ab0c63ebdfdca63c0818a8 /opcodes | |
| parent | e5a764c49c138d9409a807698d853225a4c8351f (diff) | |
| download | fsf-binutils-gdb-4ab90a7a90ccf8a671f139c1c6387ba8028e6011.zip fsf-binutils-gdb-4ab90a7a90ccf8a671f139c1c6387ba8028e6011.tar.gz fsf-binutils-gdb-4ab90a7a90ccf8a671f139c1c6387ba8028e6011.tar.bz2 | |
Fixes for unpredictable nops and 26-bit versions of teq,tst,cmn,cmp.
opcodes * arm-dis.c (print_insn_arm): Disassembling for all targets V6
and higher with ARM instruction set will now mark the 26-bit
versions of teq,tst,cmn and cmp as UNPREDICTABLE.
(arm_opcodes): Fix for unpredictable nop being recognized as a teq.
test * gas/arm/nops.d: New.
* gas/arm/nops.s: New.
* gas/arm/inst.d: Changed expectation file for 26-bit teq,
tst, cmn and cmp.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 14 |
2 files changed, 19 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ac0b433..25892ea 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> + + * arm-dis.c (print_insn_arm): Disassembling for all targets V6 + and higher with ARM instruction set will now mark the 26-bit + versions of teq,tst,cmn and cmp as UNPREDICTABLE. + (arm_opcodes): Fix for unpredictable nop being recognized as a + teq. + 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> * micromips-opc.c (micromips_opcodes): Re-order table so that move diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 46bda78..430da08 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1647,6 +1647,8 @@ static const struct opcode32 arm_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff050, 0xfffffff0, "dmb\t%U"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff040, 0xfffffff0, "dsb\t%U"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), 0xf57ff060, 0xfffffff0, "isb\t%U"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), + 0x0320f000, 0x0fffffff, "nop%c\t{%0-7d}"}, /* ARM V6T2 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), @@ -2124,11 +2126,13 @@ static const struct opcode32 arm_opcodes[] = 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"}, + 0x03300000, 0x0ff00000, "teq%p%c\t%16-19r, %o"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"}, + 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), - 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"}, + 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"}, + {ARM_FEATURE_CORE_LOW (ARM_EXT_V5), + 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"}, @@ -2277,6 +2281,8 @@ static const struct opcode32 arm_opcodes[] = 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, /* The rest. */ + {ARM_FEATURE_CORE_LOW (ARM_EXT_V7), + 0x03200000, 0x0fff00ff, "nop%c\t{%0-7d}" UNPREDICTABLE_INSTRUCTION}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V1), 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION}, {ARM_FEATURE_CORE_LOW (0), @@ -4655,6 +4661,8 @@ print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given) if (! ARM_CPU_HAS_FEATURE (private_data->features, \ arm_ext_v6)) func (stream, "p"); + else + is_unpredictable = TRUE; } break; |