diff options
author | Nick Clifton <nickc@redhat.com> | 2003-06-05 16:04:20 +0000 |
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committer | Nick Clifton <nickc@redhat.com> | 2003-06-05 16:04:20 +0000 |
commit | 36c3ae2457c89d404e9bb81de084da39064ce7cc (patch) | |
tree | 8fc0752722e1a7e4458e19310a686ac2679a9621 /opcodes | |
parent | e5379b03cf80d6b0bd9a8d7dd03e2220a61956a2 (diff) | |
download | fsf-binutils-gdb-36c3ae2457c89d404e9bb81de084da39064ce7cc.zip fsf-binutils-gdb-36c3ae2457c89d404e9bb81de084da39064ce7cc.tar.gz fsf-binutils-gdb-36c3ae2457c89d404e9bb81de084da39064ce7cc.tar.bz2 |
Add code to handle even-numbered only register operands
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 12 | ||||
-rw-r--r-- | opcodes/frv-asm.c | 31 | ||||
-rw-r--r-- | opcodes/frv-desc.c | 86 | ||||
-rw-r--r-- | opcodes/frv-desc.h | 13 | ||||
-rw-r--r-- | opcodes/frv-dis.c | 9 | ||||
-rw-r--r-- | opcodes/frv-ibld.c | 54 | ||||
-rw-r--r-- | opcodes/frv-opc.c | 274 | ||||
-rw-r--r-- | opcodes/frv-opc.h | 7 | ||||
-rw-r--r-- | opcodes/po/opcodes.pot | 60 |
9 files changed, 364 insertions, 182 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 5f866e4..8200278 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,18 @@ +2003-06-03 Nick Clifton <nickc@redhat.com> + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-asm.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.h: Regenerate. + * po/opcodes.pot: Regenerate. + 2003-06-03 Michael Snyder <msnyder@redhat.com> and Bernd Schmidt <bernds@redhat.com> and Alexandre Oliva <aoliva@redhat.com> + * disassemble.c (disassembler): Add support for h8300sx. * h8300-dis.c: Ditto. diff --git a/opcodes/frv-asm.c b/opcodes/frv-asm.c index 538ed2d..b4647b1 100644 --- a/opcodes/frv-asm.c +++ b/opcodes/frv-asm.c @@ -64,6 +64,8 @@ static const char * parse_s12 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); static const char * parse_u12 PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +static const char * parse_even_register + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); static const char * parse_ulo16 (cd, strp, opindex, valuep) @@ -346,6 +348,26 @@ parse_u12 (cd, strp, opindex, valuep) } } +static const char * +parse_even_register (cd, strP, tableP, valueP) + CGEN_CPU_DESC cd; + const char ** strP; + CGEN_KEYWORD * tableP; + long * valueP; +{ + const char * errmsg; + const char * saved_star_strP = * strP; + + errmsg = cgen_parse_keyword (cd, strP, tableP, valueP); + + if (errmsg == NULL && ((* valueP) & 1)) + { + errmsg = _("register number must be even"); + * strP = saved_star_strP; + } + + return errmsg; +} /* -- */ const char * frv_cgen_parse_operand @@ -455,12 +477,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields) case FRV_OPERAND_FRINTI : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRi); + break; case FRV_OPERAND_FRINTJ : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); + break; case FRV_OPERAND_FRINTK : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = parse_even_register (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRk); + break; case FRV_OPERAND_FRJ : errmsg = cgen_parse_keyword (cd, strp, & frv_cgen_opval_fr_names, & fields->f_FRj); break; diff --git a/opcodes/frv-desc.c b/opcodes/frv-desc.c index 4ad4284..ffb0b27 100644 --- a/opcodes/frv-desc.c +++ b/opcodes/frv-desc.c @@ -2173,6 +2173,18 @@ const CGEN_OPERAND frv_cgen_operand_table[] = { "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24, { 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } }, { 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } }, +/* FRintieven: (even) source register 1 */ + { "FRintieven", FRV_OPERAND_FRINTIEVEN, HW_H_FR_INT, 17, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRI] } }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintjeven: (even) source register 2 */ + { "FRintjeven", FRV_OPERAND_FRINTJEVEN, HW_H_FR_INT, 5, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRJ] } }, + { 0, { (1<<MACH_BASE) } } }, +/* FRintkeven: (even) target register */ + { "FRintkeven", FRV_OPERAND_FRINTKEVEN, HW_H_FR_INT, 30, 6, + { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_FRK] } }, + { 0, { (1<<MACH_BASE) } } }, /* d12: 12 bit signed immediate */ { "d12", FRV_OPERAND_D12, HW_H_SINT, 11, 12, { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_D12] } }, @@ -5472,7 +5484,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ +/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5497,7 +5509,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MSRAHI, "msrahi", "msrahi", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdrotli$pack $FRinti,$s6,$FRintk */ +/* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5517,7 +5529,7 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MSATHS, "msaths", "msaths", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, -/* mqsaths$pack $FRinti,$FRintj,$FRintk */ +/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32, { 0, { (1<<MACH_FR400), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_NONE } } @@ -5582,42 +5594,42 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_1 } } }, -/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } }, -/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_1 } } @@ -5682,32 +5694,32 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32, { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32, { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } @@ -5742,37 +5754,37 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ +/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ +/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, -/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } }, -/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32, { 0, { (1<<MACH_FR400), UNIT_FM0, FR400_MAJOR_M_2, FR500_MAJOR_NONE } } @@ -5817,22 +5829,22 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_4 } } }, -/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } }, -/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_4 } } @@ -5847,12 +5859,12 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mexpdhd$pack $FRinti,$u6,$FRintk */ +/* mexpdhd$pack $FRinti,$u6,$FRintkeven */ { FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ +/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } @@ -5862,37 +5874,37 @@ static const CGEN_IBASE frv_cgen_insn_table[MAX_INSNS] = FRV_INSN_MPACKH, "mpackh", "mpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2 } } }, -/* mdpackh$pack $FRinti,$FRintj,$FRintk */ +/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ { FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5 } } }, -/* munpackh$pack $FRinti,$FRintk */ +/* munpackh$pack $FRinti,$FRintkeven */ { FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* mdunpackh$pack $FRinti,$FRintk */ +/* mdunpackh$pack $FRintieven,$FRintk */ { FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32, { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7 } } }, -/* mbtoh$pack $FRintj,$FRintk */ +/* mbtoh$pack $FRintj,$FRintkeven */ { FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ { FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* mhtob$pack $FRintj,$FRintk */ +/* mhtob$pack $FRintjeven,$FRintk */ { FRV_INSN_MHTOB, "mhtob", "mhtob", 32, { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } }, -/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ { FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32, { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2 } } diff --git a/opcodes/frv-desc.h b/opcodes/frv-desc.h index 53cad79..3ecf091 100644 --- a/opcodes/frv-desc.h +++ b/opcodes/frv-desc.h @@ -677,15 +677,16 @@ typedef enum cgen_operand_type { , FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND , FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI , FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_A, FRV_OPERAND_AE - , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_D12, FRV_OPERAND_S12 - , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16 - , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS - , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA - , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX + , FRV_OPERAND_LABEL16, FRV_OPERAND_LABEL24, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN + , FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12 + , FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16 + , FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET + , FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT + , FRV_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 77 +#define MAX_OPERANDS 80 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 8 diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index f71e1c5..dfe053d 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -230,12 +230,21 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length) case FRV_OPERAND_FRINTI : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); break; + case FRV_OPERAND_FRINTIEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRi, 0); + break; case FRV_OPERAND_FRINTJ : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); break; + case FRV_OPERAND_FRINTJEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); + break; case FRV_OPERAND_FRINTK : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); break; + case FRV_OPERAND_FRINTKEVEN : + print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRk, 0); + break; case FRV_OPERAND_FRJ : print_keyword (cd, info, & frv_cgen_opval_fr_names, fields->f_FRj, 0); break; diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index 316b2cc..bac1837 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -651,12 +651,21 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc) case FRV_OPERAND_FRINTI : errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTIEVEN : + errmsg = insert_normal (cd, fields->f_FRi, 0, 0, 17, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRINTJ : errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTJEVEN : + errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRINTK : errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); break; + case FRV_OPERAND_FRINTKEVEN : + errmsg = insert_normal (cd, fields->f_FRk, 0, 0, 30, 6, 32, total_length, buffer); + break; case FRV_OPERAND_FRJ : errmsg = insert_normal (cd, fields->f_FRj, 0, 0, 5, 6, 32, total_length, buffer); break; @@ -942,12 +951,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc) case FRV_OPERAND_FRINTI : length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); break; + case FRV_OPERAND_FRINTIEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 6, 32, total_length, pc, & fields->f_FRi); + break; case FRV_OPERAND_FRINTJ : length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); break; + case FRV_OPERAND_FRINTJEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); + break; case FRV_OPERAND_FRINTK : length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); break; + case FRV_OPERAND_FRINTKEVEN : + length = extract_normal (cd, ex_info, insn_value, 0, 0, 30, 6, 32, total_length, pc, & fields->f_FRk); + break; case FRV_OPERAND_FRJ : length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_FRj); break; @@ -1216,12 +1234,21 @@ frv_cgen_get_int_operand (cd, opindex, fields) case FRV_OPERAND_FRINTI : value = fields->f_FRi; break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; case FRV_OPERAND_FRINTJ : value = fields->f_FRj; break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; case FRV_OPERAND_FRINTK : value = fields->f_FRk; break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; case FRV_OPERAND_FRJ : value = fields->f_FRj; break; @@ -1441,12 +1468,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields) case FRV_OPERAND_FRINTI : value = fields->f_FRi; break; + case FRV_OPERAND_FRINTIEVEN : + value = fields->f_FRi; + break; case FRV_OPERAND_FRINTJ : value = fields->f_FRj; break; + case FRV_OPERAND_FRINTJEVEN : + value = fields->f_FRj; + break; case FRV_OPERAND_FRINTK : value = fields->f_FRk; break; + case FRV_OPERAND_FRINTKEVEN : + value = fields->f_FRk; + break; case FRV_OPERAND_FRJ : value = fields->f_FRj; break; @@ -1675,12 +1711,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value) case FRV_OPERAND_FRINTI : fields->f_FRi = value; break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; case FRV_OPERAND_FRINTJ : fields->f_FRj = value; break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; case FRV_OPERAND_FRINTK : fields->f_FRk = value; break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; case FRV_OPERAND_FRJ : fields->f_FRj = value; break; @@ -1897,12 +1942,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value) case FRV_OPERAND_FRINTI : fields->f_FRi = value; break; + case FRV_OPERAND_FRINTIEVEN : + fields->f_FRi = value; + break; case FRV_OPERAND_FRINTJ : fields->f_FRj = value; break; + case FRV_OPERAND_FRINTJEVEN : + fields->f_FRj = value; + break; case FRV_OPERAND_FRINTK : fields->f_FRk = value; break; + case FRV_OPERAND_FRINTKEVEN : + fields->f_FRk = value; + break; case FRV_OPERAND_FRJ : fields->f_FRj = value; break; diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 545056b..de27a43 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -1033,10 +1033,18 @@ static const CGEN_IFMT ifmt_mcuti = { 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } }; +static const CGEN_IFMT ifmt_mdcutssi = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mdrotli = { 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_S6) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqsaths = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mcmpsh = { 32, 32, 0x79fc0fc0, { { F (F_PACK) }, { F (F_COND_NULL) }, { F (F_FCCK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; @@ -1045,6 +1053,10 @@ static const CGEN_IFMT ifmt_mabshs = { 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_cmqaddhss = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_maddaccs = { 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } } }; @@ -1057,6 +1069,14 @@ static const CGEN_IFMT ifmt_cmmulhs = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqmulhs = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmulhs = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mmachu = { 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } }; @@ -1065,18 +1085,54 @@ static const CGEN_IFMT ifmt_cmmachu = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mqmachu = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmqmachu = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_ACC40UK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cmexpdhw = { 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } }; +static const CGEN_IFMT ifmt_mexpdhd = { + 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmexpdhd = { + 32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_U6) }, { 0 } } +}; + static const CGEN_IFMT ifmt_munpackh = { 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } }; +static const CGEN_IFMT ifmt_mdunpackh = { + 32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_mbtoh = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_cmbtoh = { 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } }; +static const CGEN_IFMT ifmt_mhtob = { + 32, 32, 0x1ffffc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_OPE1) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmhtob = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmbtohe = { + 32, 32, 0x1fff0c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI_NULL) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } } +}; + static const CGEN_IFMT ifmt_mclracc = { 32, 32, 0x1fdffff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_A) }, { F (F_MISC_NULL_10) }, { F (F_OPE1) }, { F (F_FRJ_NULL) }, { 0 } } }; @@ -4982,11 +5038,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, & ifmt_mcuti, { 0x1ec0bc0 } }, -/* mdcutssi$pack $ACC40Si,$s6,$FRintk */ +/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTK), 0 } }, - & ifmt_mcuti, { 0x1e00380 } + { { MNEM, OP (PACK), ' ', OP (ACC40SI), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mdcutssi, { 0x1e00380 } }, /* maveh$pack $FRinti,$FRintj,$FRintk */ { @@ -5012,10 +5068,10 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, & ifmt_mrotli, { 0x1ec02c0 } }, -/* mdrotli$pack $FRinti,$s6,$FRintk */ +/* mdrotli$pack $FRintieven,$s6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (S6), ',', OP (FRINTK), 0 } }, + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (S6), ',', OP (FRINTKEVEN), 0 } }, & ifmt_mdrotli, { 0x1e002c0 } }, /* mcplhi$pack $FRinti,$u6,$FRintk */ @@ -5036,11 +5092,11 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, & ifmt_mand, { 0x1ec0300 } }, -/* mqsaths$pack $FRinti,$FRintj,$FRintk */ +/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1e003c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1e003c0 } }, /* msathu$pack $FRinti,$FRintj,$FRintk */ { @@ -5114,53 +5170,53 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmand, { 0x1c400c0 } }, -/* mqaddhss$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0600 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0600 } }, -/* mqaddhus$pack $FRinti,$FRintj,$FRintk */ +/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0640 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0640 } }, -/* mqsubhss$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0680 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0680 } }, -/* mqsubhus$pack $FRinti,$FRintj,$FRintk */ +/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec06c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec06c0 } }, -/* cmqaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0000 } }, -/* cmqaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0040 } }, -/* cmqsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc0080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc0080 } }, -/* cmqsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */ +/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmand, { 0x1cc00c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqaddhss, { 0x1cc00c0 } }, /* maddaccs$pack $ACC40Si,$ACC40Sk */ { @@ -5234,41 +5290,41 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmulhs, { 0x1c80040 } }, -/* mqmulhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0700 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0700 } }, -/* mqmulhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0740 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0740 } }, -/* mqmulxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0a80 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0a80 } }, -/* mqmulxhu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0ac0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0ac0 } }, -/* cmqmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00000 } }, -/* cmqmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00040 } }, /* mmachs$pack $FRinti,$FRintj,$ACC40Sk */ { @@ -5306,47 +5362,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmachu, { 0x1c800c0 } }, -/* mqmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0780 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0780 } }, -/* mqmachu$pack $FRinti,$FRintj,$ACC40Uk */ +/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), 0 } }, - & ifmt_mmachu, { 0x1ec07c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), 0 } }, + & ifmt_mqmachu, { 0x1ec07c0 } }, -/* cmqmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */ +/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmulhs, { 0x1d00080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmulhs, { 0x1d00080 } }, -/* cmqmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */ +/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmmachu, { 0x1d000c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40UK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmqmachu, { 0x1d000c0 } }, -/* mqxmachs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00000 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00000 } }, -/* mqxmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00040 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00040 } }, -/* mqmacxhs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1e00080 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1e00080 } }, /* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ { @@ -5396,29 +5452,29 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmmulhs, { 0x1d400c0 } }, -/* mqcpxrs$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0900 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0900 } }, -/* mqcpxru$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0940 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0940 } }, -/* mqcpxis$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec0980 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec0980 } }, -/* mqcpxiu$pack $FRinti,$FRintj,$ACC40Sk */ +/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (ACC40SK), 0 } }, - & ifmt_mmulhs, { 0x1ec09c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (ACC40SK), 0 } }, + & ifmt_mqmulhs, { 0x1ec09c0 } }, /* mexpdhw$pack $FRinti,$u6,$FRintk */ { @@ -5432,17 +5488,17 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmexpdhw, { 0x1d80080 } }, -/* mexpdhd$pack $FRinti,$u6,$FRintk */ +/* mexpdhd$pack $FRinti,$u6,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), 0 } }, - & ifmt_mrotli, { 0x1ec0cc0 } + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mexpdhd, { 0x1ec0cc0 } }, -/* cmexpdhd$pack $FRinti,$u6,$FRintk,$CCi,$cond */ +/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmexpdhw, { 0x1d800c0 } + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (U6), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmexpdhd, { 0x1d800c0 } }, /* mpackh$pack $FRinti,$FRintj,$FRintk */ { @@ -5450,47 +5506,47 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, & ifmt_mand, { 0x1ec0d00 } }, -/* mdpackh$pack $FRinti,$FRintj,$FRintk */ +/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mand, { 0x1ec0d80 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mqsaths, { 0x1ec0d80 } }, -/* munpackh$pack $FRinti,$FRintk */ +/* munpackh$pack $FRinti,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, + { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTKEVEN), 0 } }, & ifmt_munpackh, { 0x1ec0d40 } }, -/* mdunpackh$pack $FRinti,$FRintk */ +/* mdunpackh$pack $FRintieven,$FRintk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTI), ',', OP (FRINTK), 0 } }, - & ifmt_munpackh, { 0x1ec0dc0 } + { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mdunpackh, { 0x1ec0dc0 } }, -/* mbtoh$pack $FRintj,$FRintk */ +/* mbtoh$pack $FRintj,$FRintkeven */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mabshs, { 0x1ec0e00 } + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), 0 } }, + & ifmt_mbtoh, { 0x1ec0e00 } }, -/* cmbtoh$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } }, & ifmt_cmbtoh, { 0x1dc0000 } }, -/* mhtob$pack $FRintj,$FRintk */ +/* mhtob$pack $FRintjeven,$FRintk */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), 0 } }, - & ifmt_mabshs, { 0x1ec0e40 } + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), 0 } }, + & ifmt_mhtob, { 0x1ec0e40 } }, -/* cmhtob$pack $FRintj,$FRintk,$CCi,$cond */ +/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */ { { 0, 0, 0, 0 }, - { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmbtoh, { 0x1dc0040 } + { { MNEM, OP (PACK), ' ', OP (FRINTJEVEN), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, + & ifmt_cmhtob, { 0x1dc0040 } }, /* mbtohe$pack $FRintj,$FRintk */ { @@ -5502,7 +5558,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = { { 0, 0, 0, 0 }, { { MNEM, OP (PACK), ' ', OP (FRINTJ), ',', OP (FRINTK), ',', OP (CCI), ',', OP (COND), 0 } }, - & ifmt_cmbtoh, { 0x1dc0080 } + & ifmt_cmbtohe, { 0x1dc0080 } }, /* mclracc$pack $ACC40Sk,$A */ { diff --git a/opcodes/frv-opc.h b/opcodes/frv-opc.h index 018a643..5d23cf9 100644 --- a/opcodes/frv-opc.h +++ b/opcodes/frv-opc.h @@ -27,11 +27,14 @@ with this program; if not, write to the Free Software Foundation, Inc., /* -- opc.h */ -#undef CGEN_DIS_HASH_SIZE +#undef CGEN_DIS_HASH_SIZE #define CGEN_DIS_HASH_SIZE 128 -#undef CGEN_DIS_HASH +#undef CGEN_DIS_HASH #define CGEN_DIS_HASH(buffer, value) (((value) >> 18) & 127) +/* Allows reason codes to be output when assembler errors occur. */ +#define CGEN_VERBOSE_ASSEMBLER_ERRORS + /* Vliw support. */ #define FRV_VLIW_SIZE 4 /* fr500 has largest vliw size of 4. */ typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; diff --git a/opcodes/po/opcodes.pot b/opcodes/po/opcodes.pot index 41bc747..ee61ca6 100644 --- a/opcodes/po/opcodes.pot +++ b/opcodes/po/opcodes.pot @@ -6,7 +6,7 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2003-06-03 14:31+0100\n" +"POT-Creation-Date: 2003-06-05 11:34+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -87,69 +87,69 @@ msgstr "" msgid "Address 0x%x is out of bounds.\n" msgstr "" -#: fr30-asm.c:323 frv-asm.c:595 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 #: openrisc-asm.c:244 xstormy16-asm.c:284 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:373 frv-asm.c:645 ip2k-asm.c:624 iq2000-asm.c:513 m32r-asm.c:375 +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 #: openrisc-asm.c:294 xstormy16-asm.c:334 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 -#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 ip2k-asm.c:760 ip2k-asm.c:764 -#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:649 iq2000-asm.c:653 -#: iq2000-asm.c:740 iq2000-asm.c:842 m32r-asm.c:511 m32r-asm.c:515 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 #: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 #: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470 #: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:556 frv-asm.c:828 ip2k-asm.c:807 iq2000-asm.c:696 m32r-asm.c:558 +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 #: openrisc-asm.c:477 xstormy16-asm.c:517 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:566 frv-asm.c:838 ip2k-asm.c:817 iq2000-asm.c:706 m32r-asm.c:568 +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 #: openrisc-asm.c:487 xstormy16-asm.c:527 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:594 frv-asm.c:866 ip2k-asm.c:845 iq2000-asm.c:734 m32r-asm.c:596 +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 #: openrisc-asm.c:515 xstormy16-asm.c:555 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:701 frv-asm.c:973 ip2k-asm.c:952 iq2000-asm.c:841 m32r-asm.c:703 -#: openrisc-asm.c:622 xstormy16-asm.c:662 +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:713 frv-asm.c:985 ip2k-asm.c:964 iq2000-asm.c:853 m32r-asm.c:715 -#: openrisc-asm.c:634 xstormy16-asm.c:674 +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:716 frv-asm.c:988 ip2k-asm.c:967 iq2000-asm.c:856 m32r-asm.c:718 -#: openrisc-asm.c:637 xstormy16-asm.c:677 +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:39 m32r-dis.c:41 +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 #: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:320 frv-dis.c:362 ip2k-dis.c:329 iq2000-dis.c:190 m32r-dis.c:251 +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 #: openrisc-dis.c:138 xstormy16-dis.c:171 #, c-format msgid "Unrecognized field %d while printing insn.\n" @@ -167,50 +167,54 @@ msgstr "" msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:730 frv-ibld.c:820 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 #: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:937 frv-ibld.c:1103 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 #: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1086 frv-ibld.c:1348 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 #: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1215 frv-ibld.c:1573 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 #: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1349 frv-ibld.c:1807 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 #: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1471 frv-ibld.c:2029 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 #: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:407 +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "" + +#: h8300-dis.c:377 #, c-format -msgid "Hmmmm %x" +msgid "Hmmmm 0x%x" msgstr "" -#: h8300-dis.c:418 +#: h8300-dis.c:760 #, c-format -msgid "Don't understand %x \n" +msgid "Don't understand 0x%x \n" msgstr "" #: h8500-dis.c:143 |