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| author | H.J. Lu <hjl.tools@gmail.com> | 2015-07-22 13:24:20 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2015-07-22 13:26:21 -0700 |
| commit | 20c2a615876bdf0d5dc8e2db86eea1312d9dc9b8 (patch) | |
| tree | 156526f9fed8f28581d1d741494feee7c6b92c65 /opcodes | |
| parent | 7360e63f80782cf34a195eb1c6149760c3da7f14 (diff) | |
| download | fsf-binutils-gdb-20c2a615876bdf0d5dc8e2db86eea1312d9dc9b8.zip fsf-binutils-gdb-20c2a615876bdf0d5dc8e2db86eea1312d9dc9b8.tar.gz fsf-binutils-gdb-20c2a615876bdf0d5dc8e2db86eea1312d9dc9b8.tar.bz2 | |
Fix memory operand size for vcvtt?ps2u?qq instructions
When disassembling AVX512 vcvtt?ps2u?q instructions with data
broadcasting enabled, memory operand size should be DWORD.
gas/testsuite/
PR binutils/18631
* gas/i386avx512dq-intel.d: Replace "QWORD" with "DWORD" in
vcvtt?ps2u?qq instructions disassembly regexes.
Add disassembly regex for new test.
* gas/i386/avx512dq.d: Likewise.
* gas/i386/avx512dq_vl-intel.d: Likewise.
* gas/i386/avx512dq_vl.d: Likewise.
* gas/i386/x86-64-avx512dq-intel.d: Likewise.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/x86-64-avx512dq_vl-intel.d: Likewise.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512dq.s: Add new test for Intel syntax with memory
operand and broadcasting enabled.
* gas/i386/avx512dq_vl.s: Likewise.
* gas/i386/x86-64-avx512dq.s: Likewise.
* gas/i386/x86-64-avx512dq_vl.s: Likewise.
opcodes/
PR binutils/18631
* i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
"EXEvexHalfBcstXmmq" for the second operand.
(EVEX_W_0F79_P_2): Likewise.
(EVEX_W_0F7A_P_2): Likewise.
(EVEX_W_0F7B_P_2): Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 9 | ||||
| -rw-r--r-- | opcodes/i386-dis-evex.h | 8 |
2 files changed, 13 insertions, 4 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index bcccdb3..6ba1b85 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,12 @@ +2015-07-22 Alexander Fomin <alexander.fomin@intel.com> + + PR binutils/18631 + * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with + "EXEvexHalfBcstXmmq" for the second operand. + (EVEX_W_0F79_P_2): Likewise. + (EVEX_W_0F7A_P_2): Likewise. + (EVEX_W_0F7B_P_2): Likewise. + 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> * arm-dis.c (print_insn_coprocessor): Added support for quarter diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index 551ecdf..c3283e0 100644 --- a/opcodes/i386-dis-evex.h +++ b/opcodes/i386-dis-evex.h @@ -3196,7 +3196,7 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F78_P_2 */ { - { "vcvttps2uqq", { XM, EXxmmq, EXxEVexS }, 0 }, + { "vcvttps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, { "vcvttpd2uqq", { XM, EXx, EXxEVexS }, 0 }, }, /* EVEX_W_0F79_P_0 */ @@ -3206,7 +3206,7 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F79_P_2 */ { - { "vcvtps2uqq", { XM, EXxmmq, EXxEVexR }, 0 }, + { "vcvtps2uqq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 }, { "vcvtpd2uqq", { XM, EXx, EXxEVexR }, 0 }, }, /* EVEX_W_0F7A_P_1 */ @@ -3216,7 +3216,7 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F7A_P_2 */ { - { "vcvttps2qq", { XM, EXxmmq, EXxEVexS }, 0 }, + { "vcvttps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, { "vcvttpd2qq", { XM, EXx, EXxEVexS }, 0 }, }, /* EVEX_W_0F7A_P_3 */ @@ -3231,7 +3231,7 @@ static const struct dis386 evex_table[][256] = { }, /* EVEX_W_0F7B_P_2 */ { - { "vcvtps2qq", { XM, EXxmmq, EXxEVexR }, 0 }, + { "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 }, { "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 }, }, /* EVEX_W_0F7B_P_3 */ |