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| author | Matthew Wahab <matthew.wahab@arm.com> | 2016-01-12 16:35:30 +0000 |
|---|---|---|
| committer | Matthew Wahab <matthew.wahab@arm.com> | 2016-01-12 16:41:07 +0000 |
| commit | 105bde5771c1c1b26b69e3623c88f3caafa3a480 (patch) | |
| tree | 6d847f75a404a4fe864847a023de276aaffcd8a7 /opcodes | |
| parent | ac06903dcff237777c8d507a03aafd79c84129ae (diff) | |
| download | fsf-binutils-gdb-105bde5771c1c1b26b69e3623c88f3caafa3a480.zip fsf-binutils-gdb-105bde5771c1c1b26b69e3623c88f3caafa3a480.tar.gz fsf-binutils-gdb-105bde5771c1c1b26b69e3623c88f3caafa3a480.tar.bz2 | |
[ARM] Support ARMv8.2 RAS extension.
The ARMv8.2 architecture includes the RAS extension which adds an
instruction, ESB, and a number of coprocessor registers. This patch adds
the instruction to binutils, making it available when -march=armv8.2-a
is selected. It also adds tests for the instruction and for the
coprocessor registers.
gas/
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-arm.c (arm_ext_v8_2): New.
(insns): Add "esb".
* testsuite/gas/arm/armv8_2-a.d: New.
* testsuite/gas/arm/armv8_2-a.s: New.
opcodes/
2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
* arm-dis.c (arm_opcodes): Add "esb".
(thumb_opcodes): Likewise.
Change-Id: I67f3d70789db78d1c66a56c4994675f99ac15e34
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 5 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 8 |
2 files changed, 13 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6ccfdb7..333bac5 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,8 @@ +2016-01-12 Matthew Wahab <matthew.wahab@arm.com> + + * arm-dis.c (arm_opcodes): Add "esb". + (thumb_opcodes): Likewise. + 2016-01-11 Peter Bergner <bergner@vnet.ibm.com> * ppc-opc.c <xscmpnedp>: Delete. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 2695101..56da264 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1576,6 +1576,10 @@ static const struct opcode32 arm_opcodes[] = 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"}, + /* V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A), + 0xe320f010, 0xffffffff, "esb"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0x0320f005, 0x0fffffff, "sevl"}, @@ -2532,6 +2536,10 @@ static const struct opcode32 thumb32_opcodes[] = {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"}, + /* ARM V8.2 RAS extension instructions. */ + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A), + 0xf3af8010, 0xffffffff, "esb"}, + /* V8 instructions. */ {ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xf3af8005, 0xffffffff, "sevl%c.w"}, |