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| author | Nelson Chu <nelson.chu@sifive.com> | 2023-11-24 15:46:56 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-12-01 09:29:07 +0800 |
| commit | 248bf6de04032c666cbbd8d3278efa60b6059660 (patch) | |
| tree | 2d4ddc632b91b3f3058b55d6d16868afca30472a /opcodes/riscv-dis.c | |
| parent | ea1bd007428cb20df9a36a049d3a0ccd9ae74894 (diff) | |
| download | fsf-binutils-gdb-248bf6de04032c666cbbd8d3278efa60b6059660.zip fsf-binutils-gdb-248bf6de04032c666cbbd8d3278efa60b6059660.tar.gz fsf-binutils-gdb-248bf6de04032c666cbbd8d3278efa60b6059660.tar.bz2 | |
RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.
List of instructions:
sf.vc.x
sf.vc.i
sf.vc.vv
sf.vc.xv
sf.vc.iv
sf.vc.fv
sf.vc.vvv
sf.vc.xvv
sf.vc.ivv
sf.vc.fvv
sf.vc.vvw
sf.vc.xvw
sf.vc.ivw
sf.vc.fvw
sf.vc.v.x
sf.vc.v.i
sf.vc.v.vv
sf.vc.v.xv
sf.vc.v.iv
sf.vc.v.fv
sf.vc.v.vvv
sf.vc.v.xvv
sf.vc.v.ivv
sf.vc.v.fvv
sf.vc.v.vvw
sf.vc.v.xvw
sf.vc.v.ivw
sf.vc.v.fvw
Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'opcodes/riscv-dis.c')
| -rw-r--r-- | opcodes/riscv-dis.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index f7f4c07..cb521dc 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -702,6 +702,33 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info goto undefined_modifier; } break; + case 's': /* Vendor-specific (SiFive) operands. */ + switch (*++oparg) + { + /* SiFive vector coprocessor interface. */ + case 'd': + print (info->stream, dis_style_register, "0x%x", + (unsigned) EXTRACT_OPERAND (RD, l)); + break; + case 't': + print (info->stream, dis_style_register, "0x%x", + (unsigned) EXTRACT_OPERAND (RS2, l)); + break; + case 'O': + switch (*++oparg) + { + case '2': + print (info->stream, dis_style_register, "0x%x", + (unsigned) EXTRACT_OPERAND (XSO2, l)); + break; + case '1': + print (info->stream, dis_style_register, "0x%x", + (unsigned) EXTRACT_OPERAND (XSO1, l)); + break; + } + break; + } + break; default: goto undefined_modifier; } |