diff options
| author | Alan Modra <amodra@gmail.com> | 2020-05-11 09:48:29 +0930 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2020-05-11 21:08:37 +0930 |
| commit | 9cc4ce88316e666fd5af0fbc1ea110a7dc42adb0 (patch) | |
| tree | c2f632a6e2f70fda8a879566c8b72df8bbb4a1f9 /opcodes/ppc-opc.c | |
| parent | 5d57bc3ff934df1136daa19bbec45e155114ada3 (diff) | |
| download | fsf-binutils-gdb-9cc4ce88316e666fd5af0fbc1ea110a7dc42adb0.zip fsf-binutils-gdb-9cc4ce88316e666fd5af0fbc1ea110a7dc42adb0.tar.gz fsf-binutils-gdb-9cc4ce88316e666fd5af0fbc1ea110a7dc42adb0.tar.bz2 | |
Power10 VSX load/store rightmost element operations
opcodes/
* ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
stxvrbx, stxvrhx, stxvrwx, stxvrdx.
gas/
* testsuite/gas/ppc/rightmost.d,
* testsuite/gas/ppc/rightmost.s: New test.
* testsuite/gas/ppc/ppc.exp: Run it.
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index e853b9f..9c0dd7b 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -6033,6 +6033,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, +{"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"isellt", X(31,15), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, {"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, @@ -6087,6 +6089,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, {"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, +{"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, {"iselgt", X(31,47), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, @@ -6097,6 +6101,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, +{"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"iseleq", X(31,79), X_MASK, PPCISEL, 0, {RT, RA0, RB}}, {"isel", XISEL(31,15), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, CRB}}, @@ -6185,6 +6191,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, {"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, +{"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, {"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, @@ -6229,6 +6237,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, +{"stxvrbx", X(31,141), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, {"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, @@ -6274,6 +6284,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, +{"stxvrhx", X(31,173), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, @@ -6321,6 +6333,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, {"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, +{"stxvrwx", X(31,205), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, {"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, @@ -6372,6 +6386,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, {"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, +{"stxvrdx", X(31,237), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, + {"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, {"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, {"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, |