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| author | Dmitry Selyutin <ghostmansd@gmail.com> | 2022-07-25 16:10:16 +0300 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2022-08-11 18:38:29 +0930 |
| commit | 5eafd6deb4bb5e41e3a023688ac12ad9d45cae17 (patch) | |
| tree | 1999e0c5d7aae7c3abd02ccc1d8dbe9fa8b3e61c /opcodes/ppc-opc.c | |
| parent | 59f08271dda07502f53575538efcd19d247c70e1 (diff) | |
| download | fsf-binutils-gdb-5eafd6deb4bb5e41e3a023688ac12ad9d45cae17.zip fsf-binutils-gdb-5eafd6deb4bb5e41e3a023688ac12ad9d45cae17.tar.gz fsf-binutils-gdb-5eafd6deb4bb5e41e3a023688ac12ad9d45cae17.tar.bz2 | |
ppc/svp64: support setvl instructions
https://libre-soc.org/openpower/sv/
https://libre-soc.org/openpower/sv/setvl/
https://libre-soc.org/openpower/isa/simplev/
Diffstat (limited to 'opcodes/ppc-opc.c')
| -rw-r--r-- | opcodes/ppc-opc.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 7ad5803..8032b9f 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -3825,6 +3825,18 @@ const struct powerpc_operand powerpc_operands[] = #define HH DDD + 1 { 0x3, 13, NULL, NULL, 0 }, + +#define SVi HH + 1 + { 0x3f, 9, NULL, NULL, PPC_OPERAND_NONZERO }, + +#define vf SVi + 1 + { 0x1, 6, NULL, NULL, 0 }, + +#define vs vf + 1 + { 0x1, 7, NULL, NULL, 0 }, + +#define ms vs + 1 + { 0x1, 8, NULL, NULL, 0 }, }; const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) @@ -4700,6 +4712,13 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) #define APU_RT_MASK (APU_MASK | RT_MASK) #define APU_RA_MASK (APU_MASK | RA_MASK) +/* An SVL form instruction. */ +#define SVL(op, xop, rc) \ + (OP (op) \ + | ((((uint64_t)(xop)) & 0x1f) << 1) \ + | (((uint64_t)(rc)) & 1)) +#define SVL_MASK SVL (0x3f, 0x1f, 1) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -6769,6 +6788,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, {"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, +{"setvl", SVL(22,27,0), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, +{"setvl.", SVL(22,27,1), SVL_MASK, SVP64, PPCVLE, {RT, RA, SVi, vf, vs, ms}}, + {"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}}, {"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, {"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, |