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author | Sergei Trofimovich <siarheit@google.com> | 2022-02-14 17:12:41 +0000 |
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committer | Nick Clifton <nickc@redhat.com> | 2022-02-14 17:12:41 +0000 |
commit | a532eb7277ff64fb073e209d418b0a97f686c0e3 (patch) | |
tree | 31445db26196f74696cace988a1ff6e633746329 /opcodes/microblaze-opc.h | |
parent | 660da3c14b3b1815d6b3f1849a7225a10d819042 (diff) | |
download | fsf-binutils-gdb-a532eb7277ff64fb073e209d418b0a97f686c0e3.zip fsf-binutils-gdb-a532eb7277ff64fb073e209d418b0a97f686c0e3.tar.gz fsf-binutils-gdb-a532eb7277ff64fb073e209d418b0a97f686c0e3.tar.bz2 |
microblaze: fix fsqrt collicion to build on glibc-2.35
* microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
* microblaze-opc.h: Follow 'fsqrt' rename.
Diffstat (limited to 'opcodes/microblaze-opc.h')
-rw-r--r-- | opcodes/microblaze-opc.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 81bf2e1..ffb0f08 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -268,7 +268,7 @@ const struct op_code_struct {"fcmp.un", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000200, OPCODE_MASK_H4, fcmp_un, arithmetic_inst }, {"flt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000280, OPCODE_MASK_H4, flt, arithmetic_inst }, {"fint", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000300, OPCODE_MASK_H4, fint, arithmetic_inst }, - {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, fsqrt, arithmetic_inst }, + {"fsqrt", INST_TYPE_RD_R1, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x58000380, OPCODE_MASK_H4, microblaze_fsqrt, arithmetic_inst }, {"tget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C001000, OPCODE_MASK_H32, tget, anyware_inst }, {"tcget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C003000, OPCODE_MASK_H32, tcget, anyware_inst }, {"tnget", INST_TYPE_RD_RFSL, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x6C005000, OPCODE_MASK_H32, tnget, anyware_inst }, |