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| author | Hu, Lin1 <lin1.hu@intel.com> | 2024-11-19 10:31:44 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2024-11-19 10:45:56 +0800 |
| commit | d7d71afa6aa2db0e7d598af480ed7f14157104d1 (patch) | |
| tree | e403a6c346e8d49d7d67ea275c50d936e08a66a1 /opcodes/i386-opc.tbl | |
| parent | 77bcfb741cbec8cadec7a0d450a32c8a5b161f23 (diff) | |
| download | fsf-binutils-gdb-d7d71afa6aa2db0e7d598af480ed7f14157104d1.zip fsf-binutils-gdb-d7d71afa6aa2db0e7d598af480ed7f14157104d1.tar.gz fsf-binutils-gdb-d7d71afa6aa2db0e7d598af480ed7f14157104d1.tar.bz2 | |
Support x86 Intel MSR_IMM
gas/ChangeLog:
* NEWS: Support x86 Intel MSR_IMM.
* config/tc-i386.c (cpu_arch): Add MSR_IMM.
(cpu_flags_match): Add MSR_IMM to APX_F related processing.
(i386_assemble): WRMSRNS's first operand is imm32, so add
MN_wrmsrns like MN_uwrmsr.
* doc/c-i386.texi: Document .msr_imm.
* testsuite/gas/i386/i386.exp: Run MSR_IMM tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/msr_imm-inval.l: New test.
* testsuite/gas/i386/msr_imm-inval.s: Ditto.
* testsuite/gas/i386/x86-64-msr_imm-intel.d: Ditto.
* testsuite/gas/i386/x86-64-msr_imm.d: Ditto.
* testsuite/gas/i386/x86-64-msr_imm.s: Ditto.
opcodes/ChangeLog:
* i386-dis.c: Add REG_VEX_MAP7_F6_L_0_W_0,
PREFIX_VEX_MAP7_F6_L_0_W_0_R_0_X86_64,
X86_64_VEX_MAP7_F6_L_0_W_0_R_0,
VEX_LEN_MAP7_F6,
VEX_W_MAP7_F6_L_0.
(reg_table): New entry for MSR_IMM.
(prefix_table): Ditto.
(x86_64_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(map7_f6_opcode): New variable for MAP7.
(get_valid_dis386): Support MAP7.
* i386-gen.c (cpu_flags): Add MSR_IMM.
* i386-init.h: Regenerated.
* i386-mnem.h: Ditto.
* i386-opc.h (i386_cpu_flags): Add cpumsr_imm.
* i386-opc.tbl: Add MSR_IMM instructions.
* i386-tbl.h: Regenerated.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index c786b7e..7107317 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3421,6 +3421,14 @@ uwrmsr, 0xf3f8/0, APX_F(USER_MSR), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm3 // USER_MSR instructions end. +// MSR_IMM instructions. + +rdmsr, 0xf2f6/0, APX_F(MSR_IMM), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } +// See uwrmsr for the unusual Imm32. +wrmsrns, 0xf3f6/0, APX_F(MSR_IMM), Modrm|Vex128|Map7|EVex128|VexW0|NoSuf, { Imm32, Reg64 } + +// MSR_IMM instructions end. + // APX Push2/Pop2 instructions. //PUSH2/POP2 pushes/pops 2 GPRs at a time to/from the stack. So 2 GPRs are both //Dst/Src, here the V register is used to encode the Operand 1 (Intel format). |