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| author | Kong Lingling <lingling.kong@intel.com> | 2024-12-03 15:34:05 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2024-12-03 15:34:05 +0800 |
| commit | 98439a80cce3ba652ef4bd4cc69c0b7a04c2c60e (patch) | |
| tree | c728982c5a76b97868109fb20f58e06321c046b0 /opcodes/i386-opc.tbl | |
| parent | 57722967554367f0a0f5482c54206f2c94c00433 (diff) | |
| download | fsf-binutils-gdb-98439a80cce3ba652ef4bd4cc69c0b7a04c2c60e.zip fsf-binutils-gdb-98439a80cce3ba652ef4bd4cc69c0b7a04c2c60e.tar.gz fsf-binutils-gdb-98439a80cce3ba652ef4bd4cc69c0b7a04c2c60e.tar.bz2 | |
Support Intel AVX10.2 BF16 instructions
In this patch, we will support AVX10.2 BF16 instructions. All of them
are new instructions forms. In current documentation, it is still
VSCALEFPBF16, but it will change to VSCALEFNEPBF16 eventually.
In disassembler part, we added %XB to reduce W table pass since all
of them get evex.w=0.
gas/Changelog:
* testsuite/gas/i386/i386.exp: Add AVX10.2 tests.
* testsuite/gas/i386/x86-64.exp: Ditto.
* testsuite/gas/i386/avx10_2-256-bf16-intel.d: New.
* testsuite/gas/i386/avx10_2-256-bf16.d: Ditto.
* testsuite/gas/i386/avx10_2-256-bf16.s: Ditto.
* testsuite/gas/i386/avx10_2-512-bf16-intel.d: Ditto.
* testsuite/gas/i386/avx10_2-512-bf16.d: Ditto.
* testsuite/gas/i386/avx10_2-512-bf16.s: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-bf16-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-bf16.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-256-bf16.s: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-512-bf16-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-512-bf16.d: Ditto.
* testsuite/gas/i386/x86-64-avx10_2-512-bf16.s: Ditto.
opcodes/
* i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3AC2,
PREFIX_EVEX_MAP5_2F, PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58,
PREFIX_EVEX_MAP5_59, PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D,
PREFIX_EVEX_MAP5_5E, PREFIX_EVEX_MAP5_5F.
Add PREFIX_EVEX_MAP6_2C, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E,
PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C,
PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA,
PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8,
PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE.
* i386-dis-evex.h (evex_table): Update PREFIX_EVEX_MAP6_2C,
PREFIX_EVEX_MAP6_42, PREFIX_EVEX_MAP6_4C, PREFIX_EVEX_MAP6_4E,
PREFIX_EVEX_MAP6_98, PREFIX_EVEX_MAP6_9A, PREFIX_EVEX_MAP6_9C,
PREFIX_EVEX_MAP6_9E, PREFIX_EVEX_MAP6_A8, PREFIX_EVEX_MAP6_AA,
PREFIX_EVEX_MAP6_AC, PREFIX_EVEX_MAP6_AE, PREFIX_EVEX_MAP6_B8,
PREFIX_EVEX_MAP6_BA, PREFIX_EVEX_MAP6_BC, PREFIX_EVEX_MAP6_BE.
* i386-dis.c (PREFIX_EVEX_MAP6_2C): New enum.
(PREFIX_EVEX_MAP6_42): Ditto.
(PREFIX_EVEX_MAP6_4C): Ditto.
(PREFIX_EVEX_MAP6_4E): Ditto.
(PREFIX_EVEX_MAP6_98): Ditto.
(PREFIX_EVEX_MAP6_9A): Ditto.
(PREFIX_EVEX_MAP6_9C): Ditto.
(PREFIX_EVEX_MAP6_9E): Ditto.
(PREFIX_EVEX_MAP6_A8): Ditto.
(PREFIX_EVEX_MAP6_AA): Ditto.
(PREFIX_EVEX_MAP6_AC): Ditto.
(PREFIX_EVEX_MAP6_AE): Ditto.
(PREFIX_EVEX_MAP6_B8): Ditto.
(PREFIX_EVEX_MAP6_BA): Ditto.
(PREFIX_EVEX_MAP6_BC): Ditto.
(PREFIX_EVEX_MAP6_BE): Ditto.
(putop): Handle %XB.
* i386-opc.tbl: Add AVX10.2 instructions.
* i386-mnem.h: Regenerated.
* i386-tbl.h: Ditto.
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 8adf6a2..e62ce3f 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3464,4 +3464,24 @@ vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|No vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } vcvthf82ph, 0xf21e, AVX10_2, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +v<fop><fop:ne>pbf16, 0x66<fop:opc>, AVX10_2, Modrm|Map5|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +v<fm><fma>nepbf16, 0x<fm:opc3> | 0x<fma:opc>, AVX10_2, Modrm|Map6|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vcmppbf16, 0xf2c2, AVX10_2, Modrm|Space0F3A|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vfpclasspbf16, 0xf266, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8ShiftVL|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|BaseIndex, RegMask } +vfpclasspbf16x, 0xf266, AVX10_2, Modrm|Space0F3A|EVex128|VexW0|Masking|Disp8MemShift=4|NoSuf|ATTSyntax, { Imm8, RegXMM|Unspecified|BaseIndex, RegMask } +vfpclasspbf16y, 0xf266, AVX10_2, Modrm|Space0F3A|EVex256|VexW0|Masking|Disp8MemShift=5|NoSuf|ATTSyntax, { Imm8, RegYMM|Unspecified|BaseIndex, RegMask } +vfpclasspbf16z, 0xf266, AVX10_2, Modrm|Space0F3A|EVex512|VexW0|Masking|Disp8MemShift=6|NoSuf|ATTSyntax, { Imm8, RegZMM|Unspecified|BaseIndex, RegMask } +vgetexppbf16, 0x42, AVX10_2, Modrm|Map6|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetmantpbf16, 0xf226, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcppbf16, 0x4c, AVX10_2, Modrm|Map6|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vreducenepbf16, 0xf256, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrndscalenepbf16, 0xf208, AVX10_2, Modrm|Space0F3A|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrtpbf16, 0x4e, AVX10_2, Modrm|Map6|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vscalefnepbf16, 0x2c, AVX10_2, Modrm|Map6|Src1VVVV|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vsqrtnepbf16, 0x6651, AVX10_2, Modrm|Map5|VexW0|Masking|Broadcast|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcomsbf16, 0x662f, AVX10_2, Modrm|Map5|EVexLIG|VexW0|Disp8MemShift=1|NoSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } + // AVX10.2 instructions end. |