diff options
| author | Jan Beulich <jbeulich@suse.com> | 2024-10-29 08:08:50 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-10-29 08:08:50 +0100 |
| commit | 5168ed9912e3a090a7964db99159abdf6d27ef9e (patch) | |
| tree | ef11b4f4a4ee2aabd5d63042184acd22273be2d7 /opcodes/i386-opc.tbl | |
| parent | c1a4b47e2a3016ae9144f701319c529b340dec75 (diff) | |
| download | fsf-binutils-gdb-5168ed9912e3a090a7964db99159abdf6d27ef9e.zip fsf-binutils-gdb-5168ed9912e3a090a7964db99159abdf6d27ef9e.tar.gz fsf-binutils-gdb-5168ed9912e3a090a7964db99159abdf6d27ef9e.tar.bz2 | |
x86: use <xyz> for VFPCLASSP{S,D}
Just like VFPCLASSPH does. While the order of generated table entries
changes this way, the individual entries don't change.
Diffstat (limited to 'opcodes/i386-opc.tbl')
| -rw-r--r-- | opcodes/i386-opc.tbl | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2717049..4728802 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -2832,11 +2832,7 @@ vextracti64x2, 0x6639, AVX512DQ, Modrm|Masking|Space0F3A|VexW=2|Disp8MemShift=4| vinsertf64x2, 0x6618, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } vinserti64x2, 0x6638, AVX512DQ, Modrm|Masking|Space0F3A|Src1VVVV|VexW1|Disp8MemShift=4|CheckOperandSize|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|IntelSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>, 0x6666, AVX512DQ, Modrm|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8ShiftVL|NoSuf|ATTSyntax, { Imm8|Imm8S, RegXMM|RegYMM|RegZMM|<sd:elem>|BaseIndex, RegMask } -vfpclassp<sd>z, 0x6666, AVX512DQ, Modrm|EVex512|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=6|NoSuf, { Imm8|Imm8S, RegZMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>x, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex128|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=4|NoSuf, { Imm8|Imm8S, RegXMM|<sd:elem>|Unspecified|BaseIndex, RegMask } -vfpclassp<sd>y, 0x6666, AVX512DQ&AVX512VL, Modrm|EVex256|Masking|Space0F3A|<sd:vexw>|Broadcast|Disp8MemShift=5|NoSuf, { Imm8|Imm8S, RegYMM|<sd:elem>|Unspecified|BaseIndex, RegMask } +vfpclassp<sd><xyz>, 0x6666, AVX512DQ&<xyz:vl>, Modrm|<xyz:attr>|Masking|Space0F3A|<sd:vexw>|Broadcast|NoSuf, { Imm8|Imm8S, <xyz:src>|<sd:elem>, RegMask } vfpclasss<sdh>, 0x<sdh:pfx>67, <sdh:cpudq>, Modrm|EVexLIG|Masking|Space0F3A|<sdh:vexw>|Disp8MemShift|NoSuf, { Imm8|Imm8S, RegXMM|<sdh:elem>|Unspecified|BaseIndex, RegMask } vpmov<dq>2m, 0xf339, AVX512DQ, Modrm|EVexDYN|Space0F38|<dq:vexw>|NoSuf, { RegXMM|RegYMM|RegZMM, RegMask } |