x86: don't use opcode_length to identify pseudo prefixes

This is in preparation of opcode_length going away as a field in the
templates. Identify pseudo prefixes by a base opcode of zero instead:
No real prefix has an opcode of zero. This at the same time allows
dropping a curious special case from i386-gen.

Since most attributes are identical for all pseudo prefixes, take the
opportunity and also template them.

1 files changed, 11 insertions, 8 deletions

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0fe0be6..ad4a525 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -926,6 +926,17 @@ typedef struct insn_template
 #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
+/* (Fake) base opcode value for pseudo prefixes.  */
+#define PSEUDO_PREFIX 0
+
+  /* extension_opcode is the 3 bit extension for group <n> insns.
+     This field is also used to store the 8-bit opcode suffix for the
+     AMD 3DNow! instructions.
+     If this template has no extension opcode (the usual case) use None
+     Instructions */
+  unsigned short extension_opcode;
+#define None 0xffff		/* If no extension_opcode is possible.  */
+
 /* Pseudo prefixes.  */
 #define Prefix_Disp8		0	/* {disp8} */
 #define Prefix_Disp16		1	/* {disp16} */
@@ -938,14 +949,6 @@ typedef struct insn_template
 #define Prefix_REX		8	/* {rex} */
 #define Prefix_NoOptimize	9	/* {nooptimize} */
 
-  /* extension_opcode is the 3 bit extension for group <n> insns.
-     This field is also used to store the 8-bit opcode suffix for the
-     AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None
-     Instructions */
-  unsigned short extension_opcode;
-#define None 0xffff		/* If no extension_opcode is possible.  */
-
   /* Opcode length.  */
   unsigned char opcode_length;