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| author | konglin1 <lingling.kong@intel.com> | 2023-12-28 01:06:40 +0000 |
|---|---|---|
| committer | Cui, Lili <lili.cui@intel.com> | 2023-12-28 11:37:16 +0000 |
| commit | 3083f376435662c747ab946bb84e6e6698985610 (patch) | |
| tree | 8e62c5347edc6fc10f602ed98d36a439a20bd55c /opcodes/i386-dis-evex-reg.h | |
| parent | ce9cddf5dd2a614815b1d9affa67c9419599ff63 (diff) | |
| download | fsf-binutils-gdb-3083f376435662c747ab946bb84e6e6698985610.zip fsf-binutils-gdb-3083f376435662c747ab946bb84e6e6698985610.tar.gz fsf-binutils-gdb-3083f376435662c747ab946bb84e6e6698985610.tar.bz2 | |
Support APX NDD
opcodes/ChangeLog:
* opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80,
REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6,
REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF.
* opcodes/i386-dis-evex.h: Add NDD insn.
* opcodes/i386-dis.c (nd): New define.
(VexGb): Ditto.
(VexGv): Ditto.
(get_valid_dis386): Change for NDD decode.
(print_insn): Ditto.
(putop): Ditto.
(intel_operand_size): Ditto.
(OP_E_memory): Ditto.
(OP_VEX): Ditto.
* opcodes/i386-opc.h (VexVVVV_DST): New.
* opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV.
* opcodes/i386-tbl.h: Regenerated.
gas/ChangeLog:
* gas/config/tc-i386.c (operand_size_match):
Support APX NDD that the number of operands is 3.
(build_apx_evex_prefix): Change for ndd encode.
(process_operands): Ditto.
(build_modrm_byte): Ditto.
(match_template): Support swap the first two operands for
APX NDD.
* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
* testsuite/gas/i386/x86-64-pseudos.d: Add test.
* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
Diffstat (limited to 'opcodes/i386-dis-evex-reg.h')
| -rw-r--r-- | opcodes/i386-dis-evex-reg.h | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/opcodes/i386-dis-evex-reg.h b/opcodes/i386-dis-evex-reg.h index 2885063..cac3c39c 100644 --- a/opcodes/i386-dis-evex-reg.h +++ b/opcodes/i386-dis-evex-reg.h @@ -49,3 +49,57 @@ { "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, { "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA }, }, + /* REG_EVEX_MAP4_80 */ + { + { "addA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "orA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "adcA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "sbbA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "andA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "subA", { VexGb, Eb, Ib }, NO_PREFIX }, + { "xorA", { VexGb, Eb, Ib }, NO_PREFIX }, + }, + /* REG_EVEX_MAP4_81 */ + { + { "addQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "orQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "adcQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "sbbQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "andQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "subQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + { "xorQ", { VexGv, Ev, Iv }, PREFIX_NP_OR_DATA }, + }, + /* REG_EVEX_MAP4_83 */ + { + { "addQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "orQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "adcQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "sbbQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "andQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + { "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA }, + }, + /* REG_EVEX_MAP4_F6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "notA", { VexGb, Eb }, NO_PREFIX }, + { "negA", { VexGb, Eb }, NO_PREFIX }, + }, + /* REG_EVEX_MAP4_F7 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "notQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + { "negQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + }, + /* REG_EVEX_MAP4_FE */ + { + { "incA", { VexGb, Eb }, NO_PREFIX }, + { "decA", { VexGb, Eb }, NO_PREFIX }, + }, + /* REG_EVEX_MAP4_FF */ + { + { "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + { "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA }, + }, |