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authorClaudiu Zissulescu <claziss@synopsys.com>2016-05-19 12:33:17 +0200
committerClaudiu Zissulescu <claziss@synopsys.com>2016-05-23 17:32:13 +0200
commit87789e08e5cb2191af1122ed98af2d6c023b3a0a (patch)
treed4016574bb8d8d19ee8ebace67b4f825bde3f04a /opcodes/arc-tbl.h
parentc810e0b87a2084656af944fe269d8c2680ba5469 (diff)
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[ARC] Add XY registers, update neg instruction.
gas/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * config/tc-arc.c (md_begin): Add XY registers. (cpu_types): Code density is default off for ARC EM. opcodes/ 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com> * arc-tbl.h (neg): New instruction variant.
Diffstat (limited to 'opcodes/arc-tbl.h')
-rw-r--r--opcodes/arc-tbl.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/arc-tbl.h b/opcodes/arc-tbl.h
index 8751bdb..c325be6 100644
--- a/opcodes/arc-tbl.h
+++ b/opcodes/arc-tbl.h
@@ -12723,6 +12723,9 @@
/* neg<.f> a,b 00100bbb01001110FBBB000000AAAAAA. */
{ "neg", 0x204E0000, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RA, RB }, { C_F }},
+/* neg<.f> 0,b 00100bbb01001110FBBB000000111110. */
+{ "neg", 0x204E0000, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { ZA, RB }, { C_F }},
+
/* neg<.f><.cc> b,b 00100bbb11001110FBBB0000001QQQQQ. */
{ "neg", 0x20CE0020, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RBdup }, { C_F, C_CC }},