diff options
| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:17 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:17 +0100 |
| commit | 6a245d9941af0ae1681115cc2d732a031e02b4f7 (patch) | |
| tree | 311f71beaa68b79fb30be31aec36c9f70c1a8b38 /opcodes/aarch64-tbl.h | |
| parent | 7bd1d20e174fa324e02c334f8bfd1c1614233962 (diff) | |
| download | fsf-binutils-gdb-6a245d9941af0ae1681115cc2d732a031e02b4f7.zip fsf-binutils-gdb-6a245d9941af0ae1681115cc2d732a031e02b4f7.tar.gz fsf-binutils-gdb-6a245d9941af0ae1681115cc2d732a031e02b4f7.tar.bz2 | |
aarch64: Add the SVE BFMLSL instructions
This patch adds the SVE BFMLSLB and BFMLSLT instructions,
which are available when FEAT_SME2 is implemented.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index a99d2a4..6936c36 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2728,6 +2728,9 @@ static const aarch64_feature_set aarch64_feature_cssc = #define SME2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } +#define SME2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \ + { NAME, OPCODE, MASK, CLASS, OP, SME2, OPS, QUALS, \ + FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL } #define SME2_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \ { NAME, OPCODE, MASK, CLASS, OP, SME2_I16I64, OPS, QUALS, \ F_STRICT | FLAGS, 0, TIED, NULL } @@ -5357,6 +5360,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0), /* SME2 extensions to SVE2. */ + SME2_INSNC ("bfmlslb", 0x64e06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), + SME2_INSNC ("bfmlslb", 0x64e0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), + SME2_INSNC ("bfmlslt", 0x64e06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), + SME2_INSNC ("bfmlslt", 0x64e0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0), SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0), |