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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-15 12:21:33 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | 7b08cc32165912395838e7bb995d880f623fe636 (patch) | |
| tree | 0735bac1c022cf88e22f863c109f81760d71d5c6 /opcodes/aarch64-tbl.h | |
| parent | 435ad222b3de93fa647fba7221eece36b1b395eb (diff) | |
| download | fsf-binutils-gdb-7b08cc32165912395838e7bb995d880f623fe636.zip fsf-binutils-gdb-7b08cc32165912395838e7bb995d880f623fe636.tar.gz fsf-binutils-gdb-7b08cc32165912395838e7bb995d880f623fe636.tar.bz2 | |
aarch64: Add +d128 architectural feature support
Indicating the presence of the Armv9.4-a features concerning 128-bit
Page Table Descriptors, 128-bit System Registers and Instructions,
the "+d128" architectural extension flag is added to the list of
possible -march options in Binutils, together with the necessary macro
for encoding d128 instructions.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5058cc9..27550fd 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2582,6 +2582,8 @@ static const aarch64_feature_set aarch64_feature_gcs = AARCH64_FEATURE (GCS); static const aarch64_feature_set aarch64_feature_ite = AARCH64_FEATURE (ITE); +static const aarch64_feature_set aarch64_feature_d128 = + AARCH64_FEATURE (D128); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2645,6 +2647,7 @@ static const aarch64_feature_set aarch64_feature_ite = #define CHK &aarch64_feature_chk #define GCS &aarch64_feature_gcs #define ITE &aarch64_feature_ite +#define D128 &aarch64_feature_d128 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2798,6 +2801,8 @@ static const aarch64_feature_set aarch64_feature_ite = { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } #define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } +#define D128_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, ic_system, 0, D128, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ |