Use bool in opcodes

cpu/
	* frv.opc: Replace bfd_boolean with bool, FALSE with false, and
	TRUE with true throughout.
opcodes/
	* sysdep.h (POISON_BFD_BOOLEAN): Define.
	* aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
	* aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
	* aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
	* arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
	* cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
	* disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
	* i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
	* microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
	* mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
	* msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
	* ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
	* tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
	* xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
	and TRUE with true throughout.

1 files changed, 128 insertions, 128 deletions

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index eae652e..fa1612c 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -79,31 +79,31 @@ insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
 /* Operand inserters.  */
 
 /* Insert nothing.  */
-bfd_boolean
+bool
 aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		  const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
 		  aarch64_insn *code ATTRIBUTE_UNUSED,
 		  const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		  aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  return TRUE;
+  return true;
 }
 
 /* Insert register number.  */
-bfd_boolean
+bool
 aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		   aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   insert_field (self->fields[0], code, info->reg.regno, 0);
-  return TRUE;
+  return true;
 }
 
 /* Insert register number, index and/or other data for SIMD register element
    operand, e.g. the last source operand in
      SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
-bfd_boolean
+bool
 aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
 		     aarch64_insn *code, const aarch64_inst *inst,
 		     aarch64_operand_error *errors ATTRIBUTE_UNUSED)
@@ -188,11 +188,11 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
 	  assert (0);
 	}
     }
-  return TRUE;
+  return true;
 }
 
 /* Insert regno and len field of a register list operand, e.g. Vn in TBL.  */
-bfd_boolean
+bool
 aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
 		     aarch64_insn *code,
 		     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -202,12 +202,12 @@ aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
   insert_field (self->fields[0], code, info->reglist.first_regno, 0);
   /* len */
   insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Insert Rt and opcode fields for a register list operand, e.g. Vt
    in AdvSIMD load/store instructions.  */
-bfd_boolean
+bool
 aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			  const aarch64_opnd_info *info, aarch64_insn *code,
 			  const aarch64_inst *inst,
@@ -246,12 +246,12 @@ aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
     }
   insert_field (FLD_opcode, code, value, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
    single structure to all lanes instructions.  */
-bfd_boolean
+bool
 aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst,
@@ -272,12 +272,12 @@ aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
     value = (aarch64_insn) 1;
   insert_field (FLD_S, code, value, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
    operand e.g. Vt in AdvSIMD load/store single element instructions.  */
-bfd_boolean
+bool
 aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			   const aarch64_opnd_info *info, aarch64_insn *code,
 			   const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -321,13 +321,13 @@ aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
   gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
   insert_field_2 (&field, code, opcodeh2, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Insert fields immh:immb and/or Q for e.g. the shift immediate in
    SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
    or SSHR <V><d>, <V><n>, #<shift>.  */
-bfd_boolean
+bool
 aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			       const aarch64_opnd_info *info,
 			       aarch64_insn *code, const aarch64_inst *inst,
@@ -377,12 +377,12 @@ aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
     imm = info->imm.value + (8 << (unsigned)val);
   insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
 
-  return TRUE;
+  return true;
 }
 
 /* Insert fields for e.g. the immediate operands in
    BFM <Wd>, <Wn>, #<immr>, #<imms>.  */
-bfd_boolean
+bool
 aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		 aarch64_insn *code,
 		 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -396,12 +396,12 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
   if (operand_need_shift_by_four (self))
     imm >>= 4;
   insert_all_fields (self, code, imm);
-  return TRUE;
+  return true;
 }
 
 /* Insert immediate and its shift amount for e.g. the last operand in
      MOVZ <Wd>, #<imm16>{, LSL #<shift>}.  */
-bfd_boolean
+bool
 aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
 		      aarch64_insn *code, const aarch64_inst *inst,
 		      aarch64_operand_error *errors)
@@ -410,12 +410,12 @@ aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info
   aarch64_ins_imm (self, info, code, inst, errors);
   /* hw */
   insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
-  return TRUE;
+  return true;
 }
 
 /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
      MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}.  */
-bfd_boolean
+bool
 aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
 				  const aarch64_opnd_info *info,
 				  aarch64_insn *code,
@@ -443,7 +443,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
   insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
 
   if (kind == AARCH64_MOD_NONE)
-    return TRUE;
+    return true;
 
   /* shift amount partially in cmode */
   assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
@@ -455,7 +455,7 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
       /* For 8-bit move immediate, the optional LSL #0 does not require
 	 encoding.  */
       if (esize == 1)
-	return TRUE;
+	return true;
       amount >>= 3;
       if (esize == 4)
 	gen_sub_field (FLD_cmode, 1, 2, &field);	/* per word */
@@ -470,22 +470,22 @@ aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
     }
   insert_field_2 (&field, code, amount, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Insert fields for an 8-bit floating-point immediate.  */
-bfd_boolean
+bool
 aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		   aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   insert_all_fields (self, code, info->imm.value);
-  return TRUE;
+  return true;
 }
 
 /* Insert 1-bit rotation immediate (#90 or #270).  */
-bfd_boolean
+bool
 aarch64_ins_imm_rotate1 (const aarch64_operand *self,
 			 const aarch64_opnd_info *info,
 			 aarch64_insn *code, const aarch64_inst *inst,
@@ -494,11 +494,11 @@ aarch64_ins_imm_rotate1 (const aarch64_operand *self,
   uint64_t rot = (info->imm.value - 90) / 180;
   assert (rot < 2U);
   insert_field (self->fields[0], code, rot, inst->opcode->mask);
-  return TRUE;
+  return true;
 }
 
 /* Insert 2-bit rotation immediate (#0, #90, #180 or #270).  */
-bfd_boolean
+bool
 aarch64_ins_imm_rotate2 (const aarch64_operand *self,
 			 const aarch64_opnd_info *info,
 			 aarch64_insn *code, const aarch64_inst *inst,
@@ -507,24 +507,24 @@ aarch64_ins_imm_rotate2 (const aarch64_operand *self,
   uint64_t rot = info->imm.value / 90;
   assert (rot < 4U);
   insert_field (self->fields[0], code, rot, inst->opcode->mask);
-  return TRUE;
+  return true;
 }
 
 /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
    e.g.  SCVTF <Dd>, <Wn>, #<fbits>.  */
-bfd_boolean
+bool
 aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
 		   aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		   aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   insert_field (self->fields[0], code, 64 - info->imm.value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Insert arithmetic immediate for e.g. the last operand in
      SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}.  */
-bfd_boolean
+bool
 aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		  aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
 		  aarch64_operand_error *errors ATTRIBUTE_UNUSED)
@@ -534,18 +534,18 @@ aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
   insert_field (self->fields[0], code, value, 0);
   /* imm12 (unsigned) */
   insert_field (self->fields[1], code, info->imm.value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Common routine shared by aarch64_ins{,_inv}_limm.  INVERT_P says whether
    the operand should be inverted before encoding.  */
-static bfd_boolean
+static bool
 aarch64_ins_limm_1 (const aarch64_operand *self,
 		    const aarch64_opnd_info *info, aarch64_insn *code,
-		    const aarch64_inst *inst, bfd_boolean invert_p,
+		    const aarch64_inst *inst, bool invert_p,
 		    aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  bfd_boolean res;
+  bool res;
   aarch64_insn value;
   uint64_t imm = info->imm.value;
   int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
@@ -562,7 +562,7 @@ aarch64_ins_limm_1 (const aarch64_operand *self,
 
 /* Insert logical/bitmask immediate for e.g. the last operand in
      ORR <Wd|WSP>, <Wn>, #<imm>.  */
-bfd_boolean
+bool
 aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
 		  aarch64_insn *code, const aarch64_inst *inst,
 		  aarch64_operand_error *errors ATTRIBUTE_UNUSED)
@@ -572,18 +572,18 @@ aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
 }
 
 /* Insert a logical/bitmask immediate for the BIC alias of AND (etc.).  */
-bfd_boolean
+bool
 aarch64_ins_inv_limm (const aarch64_operand *self,
 		      const aarch64_opnd_info *info, aarch64_insn *code,
 		      const aarch64_inst *inst,
 		      aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
-  return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors);
+  return aarch64_ins_limm_1 (self, info, code, inst, true, errors);
 }
 
 /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
    or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>.  */
-bfd_boolean
+bool
 aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
 		aarch64_insn *code, const aarch64_inst *inst,
 		aarch64_operand_error *errors)
@@ -616,11 +616,11 @@ aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
       insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
     }
 
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}].  */
-bfd_boolean
+bool
 aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -628,12 +628,12 @@ aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
 {
   /* Rn */
   insert_field (FLD_Rn, code, info->addr.base_regno, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
-bfd_boolean
+bool
 aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -662,12 +662,12 @@ aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
     S = info->shifter.operator_present && info->shifter.amount_present;
   insert_field (FLD_S, code, S, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g.
      stlur <Xt>, [<Xn|SP>{, <amount>}].  */
-bfd_boolean
+bool
 aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -686,11 +686,11 @@ aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
       assert (info->addr.preind == 1 && info->addr.postind == 0);
       insert_field (self->fields[2], code, 1, 0);
     }
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!.  */
-bfd_boolean
+bool
 aarch64_ins_addr_simm (const aarch64_operand *self,
 		       const aarch64_opnd_info *info,
 		       aarch64_insn *code,
@@ -720,11 +720,11 @@ aarch64_ins_addr_simm (const aarch64_operand *self,
 	insert_field (self->fields[1], code, 1, 0);
     }
 
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}].  */
-bfd_boolean
+bool
 aarch64_ins_addr_simm10 (const aarch64_operand *self,
 			 const aarch64_opnd_info *info,
 			 aarch64_insn *code,
@@ -745,11 +745,11 @@ aarch64_ins_addr_simm10 (const aarch64_operand *self,
       assert (info->addr.preind == 1 && info->addr.postind == 0);
       insert_field (self->fields[3], code, 1, 0);
     }
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}].  */
-bfd_boolean
+bool
 aarch64_ins_addr_uimm12 (const aarch64_operand *self,
 			 const aarch64_opnd_info *info,
 			 aarch64_insn *code,
@@ -762,12 +762,12 @@ aarch64_ins_addr_uimm12 (const aarch64_operand *self,
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   /* uimm12 */
   insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the address operand for e.g.
      LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>.  */
-bfd_boolean
+bool
 aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -780,11 +780,11 @@ aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
     insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
   else
     insert_field (FLD_Rm, code, 0x1f, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>.  */
-bfd_boolean
+bool
 aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		  const aarch64_opnd_info *info, aarch64_insn *code,
 		  const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -792,11 +792,11 @@ aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
 {
   /* cond */
   insert_field (FLD_cond, code, info->cond->value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>.  */
-bfd_boolean
+bool
 aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		    const aarch64_opnd_info *info, aarch64_insn *code,
 		    const aarch64_inst *inst,
@@ -820,7 +820,7 @@ aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
 		detail->error = _("specified register cannot be read from");
 		detail->index = info->idx;
-		detail->non_fatal = TRUE;
+		detail->non_fatal = true;
 	  }
 	else if (opcode_flags == F_SYS_WRITE
 		 && sysreg_flags
@@ -829,17 +829,17 @@ aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
 		detail->error = _("specified register cannot be written to");
 		detail->index = info->idx;
-		detail->non_fatal = TRUE;
+		detail->non_fatal = true;
 	  }
      }
   /* op0:op1:CRn:CRm:op2 */
   insert_fields (code, info->sysreg.value, inst->opcode->mask, 5,
 		 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>.  */
-bfd_boolean
+bool
 aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -848,11 +848,11 @@ aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* op1:op2 */
   insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
 		 FLD_op2, FLD_op1);
-  return TRUE;
+  return true;
 }
 
 /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>.  */
-bfd_boolean
+bool
 aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		       const aarch64_opnd_info *info, aarch64_insn *code,
 		       const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -861,12 +861,12 @@ aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* op1:CRn:CRm:op2 */
   insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
 		 FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
-  return TRUE;
+  return true;
 }
 
 /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>.  */
 
-bfd_boolean
+bool
 aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		     const aarch64_opnd_info *info, aarch64_insn *code,
 		     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -874,12 +874,12 @@ aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
 {
   /* CRm */
   insert_field (FLD_CRm, code, info->barrier->value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the memory barrier option operand for DSB <option>nXS|#<imm>.  */
 
-bfd_boolean
+bool
 aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		     const aarch64_opnd_info *info, aarch64_insn *code,
 		     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -889,13 +889,13 @@ aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
      encoded in CRm<3:2>.  */
   aarch64_insn value = (info->barrier->value >> 2) - 4;
   insert_field (FLD_CRm_dsb_nxs, code, value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the prefetch operation option operand for e.g.
      PRFM <prfop>, [<Xn|SP>{, #<pimm>}].  */
 
-bfd_boolean
+bool
 aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		   const aarch64_opnd_info *info, aarch64_insn *code,
 		   const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -903,13 +903,13 @@ aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
 {
   /* prfop in Rt */
   insert_field (FLD_Rt, code, info->prfop->value, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode the hint number for instructions that alias HINT but take an
    operand.  */
 
-bfd_boolean
+bool
 aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
 		  const aarch64_opnd_info *info, aarch64_insn *code,
 		  const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -917,12 +917,12 @@ aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
 {
   /* CRm:op2.  */
   insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
-  return TRUE;
+  return true;
 }
 
 /* Encode the extended register operand for e.g.
      STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}].  */
-bfd_boolean
+bool
 aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			  const aarch64_opnd_info *info, aarch64_insn *code,
 			  const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -941,12 +941,12 @@ aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* imm3 */
   insert_field (FLD_imm3, code, info->shifter.amount, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Encode the shifted register operand for e.g.
      SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}.  */
-bfd_boolean
+bool
 aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -960,14 +960,14 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
   /* imm6 */
   insert_field (FLD_imm6, code, info->shifter.amount, 0);
 
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
    where <simm4> is a 4-bit signed value and where <factor> is 1 plus
    SELF's operand-dependent value.  fields[0] specifies the field that
    holds <base>.  <simm4> is encoded in the SVE_imm4 field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
 			       const aarch64_opnd_info *info,
 			       aarch64_insn *code,
@@ -977,14 +977,14 @@ aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
   int factor = 1 + get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
    where <simm6> is a 6-bit signed value and where <factor> is 1 plus
    SELF's operand-dependent value.  fields[0] specifies the field that
    holds <base>.  <simm6> is encoded in the SVE_imm6 field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
 			       const aarch64_opnd_info *info,
 			       aarch64_insn *code,
@@ -994,7 +994,7 @@ aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
   int factor = 1 + get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
@@ -1002,7 +1002,7 @@ aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
    SELF's operand-dependent value.  fields[0] specifies the field that
    holds <base>.  <simm9> is encoded in the concatenation of the SVE_imm6
    and imm3 fields, with imm3 being the less-significant part.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
 			       const aarch64_opnd_info *info,
 			       aarch64_insn *code,
@@ -1013,13 +1013,13 @@ aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_fields (code, info->addr.offset.imm / factor, 0,
 		 2, FLD_imm3, FLD_SVE_imm6);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
    is a 4-bit signed number and where <shift> is SELF's operand-dependent
    value.  fields[0] specifies the base register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1028,13 +1028,13 @@ aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
   int factor = 1 << get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
    is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
    value.  fields[0] specifies the base register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1043,13 +1043,13 @@ aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
   int factor = 1 << get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
    is SELF's operand-dependent value.  fields[0] specifies the base
    register field and fields[1] specifies the offset register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
 			     const aarch64_opnd_info *info, aarch64_insn *code,
 			     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1057,14 +1057,14 @@ aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
 {
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (self->fields[1], code, info->addr.offset.regno, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
    <shift> is SELF's operand-dependent value.  fields[0] specifies the
    base register field, fields[1] specifies the offset register field and
    fields[2] is a single-bit field that selects SXTW over UXTW.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
 			     const aarch64_opnd_info *info, aarch64_insn *code,
 			     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1076,13 +1076,13 @@ aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
     insert_field (self->fields[2], code, 0, 0);
   else
     insert_field (self->fields[2], code, 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
    5-bit unsigned number and where <shift> is SELF's operand-dependent value.
    fields[0] specifies the base register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1091,14 +1091,14 @@ aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
   int factor = 1 << get_operand_specific_data (self);
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
    where <modifier> is fixed by the instruction and where <msz> is a
    2-bit unsigned number.  fields[0] specifies the base register field
    and fields[1] specifies the offset register field.  */
-static bfd_boolean
+static bool
 aarch64_ext_sve_addr_zz (const aarch64_operand *self,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
@@ -1106,13 +1106,13 @@ aarch64_ext_sve_addr_zz (const aarch64_operand *self,
   insert_field (self->fields[0], code, info->addr.base_regno, 0);
   insert_field (self->fields[1], code, info->addr.offset.regno, 0);
   insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
    <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
    field and fields[1] specifies the offset register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
 			     const aarch64_opnd_info *info, aarch64_insn *code,
 			     const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1124,7 +1124,7 @@ aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
    <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
    field and fields[1] specifies the offset register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
 			      const aarch64_opnd_info *info,
 			      aarch64_insn *code,
@@ -1137,7 +1137,7 @@ aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
 /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
    <msz> is a 2-bit unsigned number.  fields[0] specifies the base register
    field and fields[1] specifies the offset register field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
 			      const aarch64_opnd_info *info,
 			      aarch64_insn *code,
@@ -1148,7 +1148,7 @@ aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
 }
 
 /* Encode an SVE ADD/SUB immediate.  */
-bfd_boolean
+bool
 aarch64_ins_sve_aimm (const aarch64_operand *self,
 		      const aarch64_opnd_info *info, aarch64_insn *code,
 		      const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1160,11 +1160,11 @@ aarch64_ins_sve_aimm (const aarch64_operand *self,
     insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256);
   else
     insert_all_fields (self, code, info->imm.value & 0xff);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE CPY/DUP immediate.  */
-bfd_boolean
+bool
 aarch64_ins_sve_asimm (const aarch64_operand *self,
 		       const aarch64_opnd_info *info, aarch64_insn *code,
 		       const aarch64_inst *inst,
@@ -1177,7 +1177,7 @@ aarch64_ins_sve_asimm (const aarch64_operand *self,
    array specifies which field to use for Zn.  MM is encoded in the
    concatenation of imm5 and SVE_tszh, with imm5 being the less
    significant part.  */
-bfd_boolean
+bool
 aarch64_ins_sve_index (const aarch64_operand *self,
 		       const aarch64_opnd_info *info, aarch64_insn *code,
 		       const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1187,11 +1187,11 @@ aarch64_ins_sve_index (const aarch64_operand *self,
   insert_field (self->fields[0], code, info->reglane.regno, 0);
   insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
 		 2, FLD_imm5, FLD_SVE_tszh);
-  return TRUE;
+  return true;
 }
 
 /* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM.  */
-bfd_boolean
+bool
 aarch64_ins_sve_limm_mov (const aarch64_operand *self,
 			  const aarch64_opnd_info *info, aarch64_insn *code,
 			  const aarch64_inst *inst,
@@ -1203,7 +1203,7 @@ aarch64_ins_sve_limm_mov (const aarch64_operand *self,
 /* Encode Zn[MM], where Zn occupies the least-significant part of the field
    and where MM occupies the most-significant part.  The operand-dependent
    value specifies the number of bits in Zn.  */
-bfd_boolean
+bool
 aarch64_ins_sve_quad_index (const aarch64_operand *self,
 			    const aarch64_opnd_info *info, aarch64_insn *code,
 			    const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1213,25 +1213,25 @@ aarch64_ins_sve_quad_index (const aarch64_operand *self,
   assert (info->reglane.regno < (1U << reg_bits));
   unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
   insert_all_fields (self, code, val);
-  return TRUE;
+  return true;
 }
 
 /* Encode {Zn.<T> - Zm.<T>}.  The fields array specifies which field
    to use for Zn.  */
-bfd_boolean
+bool
 aarch64_ins_sve_reglist (const aarch64_operand *self,
 			 const aarch64_opnd_info *info, aarch64_insn *code,
 			 const aarch64_inst *inst ATTRIBUTE_UNUSED,
 			 aarch64_operand_error *errors ATTRIBUTE_UNUSED)
 {
   insert_field (self->fields[0], code, info->reglist.first_regno, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode <pattern>{, MUL #<amount>}.  The fields array specifies which
    fields to use for <pattern>.  <amount> - 1 is encoded in the SVE_imm4
    field.  */
-bfd_boolean
+bool
 aarch64_ins_sve_scale (const aarch64_operand *self,
 		       const aarch64_opnd_info *info, aarch64_insn *code,
 		       const aarch64_inst *inst ATTRIBUTE_UNUSED,
@@ -1239,11 +1239,11 @@ aarch64_ins_sve_scale (const aarch64_operand *self,
 {
   insert_all_fields (self, code, info->imm.value);
   insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE shift left immediate.  */
-bfd_boolean
+bool
 aarch64_ins_sve_shlimm (const aarch64_operand *self,
 			const aarch64_opnd_info *info, aarch64_insn *code,
 			const aarch64_inst *inst,
@@ -1256,11 +1256,11 @@ aarch64_ins_sve_shlimm (const aarch64_operand *self,
   prev_operand = &inst->operands[info->idx - 1];
   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 8 * esize + info->imm.value);
-  return TRUE;
+  return true;
 }
 
 /* Encode an SVE shift right immediate.  */
-bfd_boolean
+bool
 aarch64_ins_sve_shrimm (const aarch64_operand *self,
 			const aarch64_opnd_info *info, aarch64_insn *code,
 			const aarch64_inst *inst,
@@ -1274,12 +1274,12 @@ aarch64_ins_sve_shrimm (const aarch64_operand *self,
   prev_operand = &inst->operands[info->idx - opnd_backshift];
   esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
   insert_all_fields (self, code, 16 * esize - info->imm.value);
-  return TRUE;
+  return true;
 }
 
 /* Encode a single-bit immediate that selects between #0.5 and #1.0.
    The fields array specifies which field to use.  */
-bfd_boolean
+bool
 aarch64_ins_sve_float_half_one (const aarch64_operand *self,
 				const aarch64_opnd_info *info,
 				aarch64_insn *code,
@@ -1290,12 +1290,12 @@ aarch64_ins_sve_float_half_one (const aarch64_operand *self,
     insert_field (self->fields[0], code, 0, 0);
   else
     insert_field (self->fields[0], code, 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode a single-bit immediate that selects between #0.5 and #2.0.
    The fields array specifies which field to use.  */
-bfd_boolean
+bool
 aarch64_ins_sve_float_half_two (const aarch64_operand *self,
 				const aarch64_opnd_info *info,
 				aarch64_insn *code,
@@ -1306,12 +1306,12 @@ aarch64_ins_sve_float_half_two (const aarch64_operand *self,
     insert_field (self->fields[0], code, 0, 0);
   else
     insert_field (self->fields[0], code, 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Encode a single-bit immediate that selects between #0.0 and #1.0.
    The fields array specifies which field to use.  */
-bfd_boolean
+bool
 aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
 				const aarch64_opnd_info *info,
 				aarch64_insn *code,
@@ -1322,7 +1322,7 @@ aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
     insert_field (self->fields[0], code, 0, 0);
   else
     insert_field (self->fields[0], code, 1, 0);
-  return TRUE;
+  return true;
 }
 
 /* Miscellaneous encoding functions.  */
@@ -2002,7 +2002,7 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
    Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
    matched operand qualifier sequence in *QLF_SEQ.  */
 
-bfd_boolean
+bool
 aarch64_opcode_encode (const aarch64_opcode *opcode,
 		       const aarch64_inst *inst_ori, aarch64_insn *code,
 		       aarch64_opnd_qualifier_t *qlf_seq,
@@ -2083,7 +2083,7 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
       if (operand_has_inserter (opnd)
 	  && !aarch64_insert_operand (opnd, info, &inst->value, inst,
 				      mismatch_detail))
-	    return FALSE;
+	    return false;
     }
 
   /* Call opcode encoders indicated by flags.  */
@@ -2097,14 +2097,14 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
   /* Run a verifier if the instruction has one set.  */
   if (opcode->verifier)
     {
-      enum err_type result = opcode->verifier (inst, *code, 0, TRUE,
+      enum err_type result = opcode->verifier (inst, *code, 0, true,
 					       mismatch_detail, insn_sequence);
       switch (result)
 	{
 	case ERR_UND:
 	case ERR_UNP:
 	case ERR_NYI:
-	  return FALSE;
+	  return false;
 	default:
 	  break;
 	}
@@ -2113,14 +2113,14 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
   /* Always run constrain verifiers, this is needed because constrains need to
      maintain a global state.  Regardless if the instruction has the flag set
      or not.  */
-  enum err_type result = verify_constraints (inst, *code, 0, TRUE,
+  enum err_type result = verify_constraints (inst, *code, 0, true,
 					     mismatch_detail, insn_sequence);
   switch (result)
     {
     case ERR_UND:
     case ERR_UNP:
     case ERR_NYI:
-      return FALSE;
+      return false;
     default:
       break;
     }
@@ -2131,5 +2131,5 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
 
   *code = inst->value;
 
-  return TRUE;
+  return true;
 }