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| author | Alice Carlotti <alice.carlotti@arm.com> | 2026-04-09 02:17:48 +0100 |
|---|---|---|
| committer | Alice Carlotti <alice.carlotti@arm.com> | 2026-04-09 15:34:46 +0100 |
| commit | 93c78ceb4ce70b525dd3dc2e0f78c7b0959cd0e8 (patch) | |
| tree | 375fd34e5aea757f9dc58e290b24a55f8d6a97bb /include/opcode | |
| parent | 254a4c9a4c64b77cee2613cd056c0237416d735f (diff) | |
| download | fsf-binutils-gdb-93c78ceb4ce70b525dd3dc2e0f78c7b0959cd0e8.tar.gz fsf-binutils-gdb-93c78ceb4ce70b525dd3dc2e0f78c7b0959cd0e8.tar.bz2 fsf-binutils-gdb-93c78ceb4ce70b525dd3dc2e0f78c7b0959cd0e8.zip | |
aarch64: Remove constraints on sysp operands
The CRn and CRm operands of sysp were unnecessarily constrained to the
ranges C8-C9 and C0-C7. This constraint has been removed from the
architecture spec, and was never implemented in LLVM, so remove it here
as well.
Additionally, add some more tests to cover the full range of valid sysp
operands, including omitting the pair of optional operands.
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/aarch64.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 79cbed433bb..2fdd3da49ce 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1497,11 +1497,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; to be optional, then we also implicitly specify (N+1)th operand to also be optional. */ #define F_OPD_PAIR_OPT (1ULL << 32) -/* This instruction does not allow the full range of values that the - width of fields in the assembler instruction would theoretically - allow. This impacts the constraints on assembly but yields no - impact on disassembly. */ -#define F_OPD_NARROW (1ULL << 33) + /* For the instruction with size[22:23] field. */ #define F_OPD_SIZE (1ULL << 34) /* RCPC3 instruction has the field of 'size'. */ @@ -1549,7 +1545,7 @@ extern const aarch64_opcode aarch64_opcode_table[]; /* As above, plus PN registers. */ #define F_INVALID_IMM_SYMS_3 (3ULL << 42) -/* Next bit is 44. */ +/* Next bit is 44, and 33 is also unused. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ |