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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2025-12-31 16:14:29 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2025-12-31 16:14:48 +0000 |
| commit | 35554f7b14c0cd1c59be64010de67d895906fb21 (patch) | |
| tree | ad42a4b7e26dcdb7fdbb20abee10223be6ad7c01 /include/opcode/tic6x-opcode-table.h | |
| parent | 6cc97da0a15465b046726d5ee75c8724e4a35086 (diff) | |
| download | fsf-binutils-gdb-35554f7b14c0cd1c59be64010de67d895906fb21.tar.gz fsf-binutils-gdb-35554f7b14c0cd1c59be64010de67d895906fb21.tar.bz2 fsf-binutils-gdb-35554f7b14c0cd1c59be64010de67d895906fb21.zip | |
arm, as: Support case incensitive VLDR/VSTR SYSREG
To be consistent with VMRS/VMSR this changes VLDR/VSTR SYSREG to support case
insensitive system register operands.
Diffstat (limited to 'include/opcode/tic6x-opcode-table.h')
0 files changed, 0 insertions, 0 deletions