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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-21 15:30:56 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-23 19:51:29 +0200 |
| commit | eb668e50036e979fb0a74821df4eee0307b44e66 (patch) | |
| tree | 11c176f3cbe8b76ecfe95258ab963bdbc69832e0 /include/opcode/riscv.h | |
| parent | 618ba27878a2c6f155eb5e1235c0484a55786a15 (diff) | |
| download | fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.zip fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.tar.gz fsf-binutils-gdb-eb668e50036e979fb0a74821df4eee0307b44e66.tar.bz2 | |
RISC-V: Add Zawrs ISA extension support
This patch adds support for the Zawrs ISA extension
("wrs.nto" and "wrs.sto" instructions).
The specification can be found here:
https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 1b329ef..dd2569f 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -385,6 +385,7 @@ enum riscv_insn_class INSN_CLASS_ZIFENCEI, INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, + INSN_CLASS_ZAWRS, INSN_CLASS_F_OR_ZFINX, INSN_CLASS_D_OR_ZDINX, INSN_CLASS_Q_OR_ZQINX, |