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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2021-05-29 03:26:32 +0200 |
| commit | 21629cf8bc2b16d3c75dff0c3f1222b714bf90c2 (patch) | |
| tree | 9e0d8099afb0614bd53bb12aa10e704c200204ec /include/opcode/d30v.h | |
| parent | b1458c4569ec9eeb077e928b0eb6b210c7eb647f (diff) | |
| download | fsf-binutils-gdb-21629cf8bc2b16d3c75dff0c3f1222b714bf90c2.zip fsf-binutils-gdb-21629cf8bc2b16d3c75dff0c3f1222b714bf90c2.tar.gz fsf-binutils-gdb-21629cf8bc2b16d3c75dff0c3f1222b714bf90c2.tar.bz2 | |
MIPS/opcodes: Properly handle ISA exclusion
Remove the hack used for MIPSr6 ISA exclusion from `cpu_is_member' and
handle the exclusion for any ISA levels properly in `opcode_is_member'.
Flatten the structure of the `if' statements there. No functional
change for the existing opcode tables.
include/
* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA
exclusion.
(opcode_is_member): Handle ISA level exclusion.
Diffstat (limited to 'include/opcode/d30v.h')
0 files changed, 0 insertions, 0 deletions