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| author | Yixuan Chen <chenyixuan@iscas.ac.cn> | 2024-07-04 17:16:59 +0800 |
|---|---|---|
| committer | Vladimir Mezentsev <vladimir.mezentsev@oracle.com> | 2024-07-10 15:16:03 -0700 |
| commit | 762c38d552abbfed97c349c5e7c8ef34119b2f5e (patch) | |
| tree | f0b1d2e5cf0b78204d6ab4d0f8c7dd8c9512a5b7 /gprofng/libcollector/unwind.c | |
| parent | 479edf0a6a61159486f14d5e62403f8769cc591d (diff) | |
| download | fsf-binutils-gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.zip fsf-binutils-gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.gz fsf-binutils-gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.bz2 | |
RISC-V:[gprofng] Minimal support gprofng for riscv.
ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
Diffstat (limited to 'gprofng/libcollector/unwind.c')
| -rw-r--r-- | gprofng/libcollector/unwind.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/gprofng/libcollector/unwind.c b/gprofng/libcollector/unwind.c index e62da04..55fa2e9 100644 --- a/gprofng/libcollector/unwind.c +++ b/gprofng/libcollector/unwind.c @@ -180,6 +180,11 @@ memory_error_func (int status ATTRIBUTE_UNUSED, bfd_vma addr ATTRIBUTE_UNUSED, #define GET_PC(ctx) (((ucontext_t*)ctx)->uc_mcontext.regs[15]) #define GET_SP(ctx) (((ucontext_t*)ctx)->uc_mcontext.regs[13]) #define GET_FP(ctx) (((ucontext_t*)ctx)->uc_mcontext.regs[14]) + +#elif ARCH(RISCV) +#define GET_PC(ctx) (((ucontext_t*)ctx)->uc_mcontext.__gregs[REG_PC]) +#define GET_SP(ctx) (((ucontext_t*)ctx)->uc_mcontext.__gregs[2]) +#define GET_FP(ctx) (((ucontext_t*)ctx)->uc_mcontext.__gregs[8]) #endif /* ARCH() */ /* @@ -234,6 +239,12 @@ typedef uint64_t __u64; context->uc_mcontext.sp = (__u64) __builtin_frame_address(0); \ } +#elif ARCH(RISCV) +#define FILL_CONTEXT(context) \ + { CALL_UTIL(getcontext)(context); \ + context->uc_mcontext.__gregs[2] = (uint64_t) __builtin_frame_address(0); \ + } + #endif /* ARCH() */ static int |