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author | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-10-28 10:43:26 +0000 |
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committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2018-10-28 10:43:26 +0000 |
commit | a3d7226832e5750211ec300c5929dc0f035a3661 (patch) | |
tree | a2bdd5c1ef37b35469f1ef221a90cedfbe211e25 /gdb | |
parent | 8fc91c409847f0d4e3e4cdac8161158fafd78636 (diff) | |
download | fsf-binutils-gdb-a3d7226832e5750211ec300c5929dc0f035a3661.zip fsf-binutils-gdb-a3d7226832e5750211ec300c5929dc0f035a3661.tar.gz fsf-binutils-gdb-a3d7226832e5750211ec300c5929dc0f035a3661.tar.bz2 |
gdb/riscv: Add back missing braces in riscv-linux-nat.c
In this commit:
commit ee67fd7f3f6ca78eede2862e309c0bcf266bbd7e
Date: Thu Oct 25 12:03:31 2018 +0100
gdb/riscv: Use correct regnum in riscv_linux_nat_target::fetch_registers
I incorrectly removed a set of braces in violation of the GDB coding
standard. This commit adds them back.
gdb/ChangeLog:
* riscv-linux-nat.c (riscv_linux_nat_target::fetch_registers):
Add missing braces. No functional change.
Diffstat (limited to 'gdb')
-rw-r--r-- | gdb/ChangeLog | 5 | ||||
-rw-r--r-- | gdb/riscv-linux-nat.c | 6 |
2 files changed, 9 insertions, 2 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index ff36b9b..6742fad 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2018-10-28 Andrew Burgess <andrew.burgess@embecosm.com> + + * riscv-linux-nat.c (riscv_linux_nat_target::fetch_registers): + Add missing braces. No functional change. + 2018-10-27 Philippe Waroquiers <philippe.waroquiers@skynet.be> * macrocmd.c (info_macro_command): Use report_unrecognized_option_error diff --git a/gdb/riscv-linux-nat.c b/gdb/riscv-linux-nat.c index c09121d..d51f6e3 100644 --- a/gdb/riscv-linux-nat.c +++ b/gdb/riscv-linux-nat.c @@ -201,8 +201,10 @@ riscv_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) if ((regnum == RISCV_CSR_MISA_REGNUM) || (regnum == -1)) - /* TODO: Need to add a ptrace call for this. */ - regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM); + { + /* TODO: Need to add a ptrace call for this. */ + regcache->raw_supply_zeroed (RISCV_CSR_MISA_REGNUM); + } /* Access to other CSRs has potential security issues, don't support them for now. */ |