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| author | Andrew Burgess <andrew.burgess@embecosm.com> | 2021-02-15 16:07:48 +0000 |
|---|---|---|
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | 2021-03-05 17:21:41 +0000 |
| commit | d782d24b3297d0eebdc3c823bd41993e5d670c88 (patch) | |
| tree | 0c294480083a2cfa40cc2770432beef83bf0150a /gdb/riscv-tdep.c | |
| parent | db6092f3aec43ea4d10efc5ff74274f04cdc0ad6 (diff) | |
| download | fsf-binutils-gdb-d782d24b3297d0eebdc3c823bd41993e5d670c88.zip fsf-binutils-gdb-d782d24b3297d0eebdc3c823bd41993e5d670c88.tar.gz fsf-binutils-gdb-d782d24b3297d0eebdc3c823bd41993e5d670c88.tar.bz2 | |
gdb/riscv: make riscv target description names global
A later commit will need the names of the RISC-V target description
features in files other than riscv-tdep.c. This commit just makes the
names global strings that can be accessed from other riscv-*.c files.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* riscv-tdep.c (riscv_feature_name_csr): Define.
(riscv_feature_name_cpu): Define.
(riscv_feature_name_fpu): Define.
(riscv_feature_name_virtual): Define.
(riscv_xreg_feature): Use riscv_feature_name_cpu.
(riscv_freg_feature): Use riscv_feature_name_fpu.
(riscv_virtual_feature): Use riscv_feature_name_virtual.
(riscv_csr_feature): Use riscv_feature_name_csr.
* riscv-tdep.h (riscv_feature_name_csr): Declare.
Diffstat (limited to 'gdb/riscv-tdep.c')
| -rw-r--r-- | gdb/riscv-tdep.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index da86ed1..ca3efaf 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -94,6 +94,12 @@ static unsigned int riscv_debug_unwinder = 0; static unsigned int riscv_debug_gdbarch = 0; +/* The names of the RISC-V target description features. */ +const char *riscv_feature_name_csr = "org.gnu.gdb.riscv.csr"; +static const char *riscv_feature_name_cpu = "org.gnu.gdb.riscv.cpu"; +static const char *riscv_feature_name_fpu = "org.gnu.gdb.riscv.fpu"; +static const char *riscv_feature_name_virtual = "org.gnu.gdb.riscv.virtual"; + /* Cached information about a frame. */ struct riscv_unwind_cache @@ -257,7 +263,7 @@ riscv_register_feature::register_info::check struct riscv_xreg_feature : public riscv_register_feature { riscv_xreg_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.cpu") + : riscv_register_feature (riscv_feature_name_cpu) { m_registers = { { RISCV_ZERO_REGNUM + 0, { "zero", "x0" } }, @@ -354,7 +360,7 @@ static const struct riscv_xreg_feature riscv_xreg_feature; struct riscv_freg_feature : public riscv_register_feature { riscv_freg_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.fpu") + : riscv_register_feature (riscv_feature_name_fpu) { m_registers = { { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" } }, @@ -482,7 +488,7 @@ static const struct riscv_freg_feature riscv_freg_feature; struct riscv_virtual_feature : public riscv_register_feature { riscv_virtual_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.virtual") + : riscv_register_feature (riscv_feature_name_virtual) { m_registers = { { RISCV_PRIV_REGNUM, { "priv" } } @@ -518,7 +524,7 @@ static const struct riscv_virtual_feature riscv_virtual_feature; struct riscv_csr_feature : public riscv_register_feature { riscv_csr_feature () - : riscv_register_feature ("org.gnu.gdb.riscv.csr") + : riscv_register_feature (riscv_feature_name_csr) { m_registers = { #define DECLARE_CSR(NAME,VALUE,CLASS,DEFINE_VER,ABORT_VER) \ |