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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-06 04:18:52 +0000 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-10-28 14:17:34 +0000 |
| commit | 83029f7ff5d571dff0190e8d92c26e032c7acd76 (patch) | |
| tree | 9284fece401f163d1ba0c721bf2cb27c009fc834 /gdb/disasm.h | |
| parent | 3190ebcbbf846617c0d5026995c26917f609a0f4 (diff) | |
| download | fsf-binutils-gdb-83029f7ff5d571dff0190e8d92c26e032c7acd76.zip fsf-binutils-gdb-83029f7ff5d571dff0190e8d92c26e032c7acd76.tar.gz fsf-binutils-gdb-83029f7ff5d571dff0190e8d92c26e032c7acd76.tar.bz2 | |
RISC-V: Fallback for instructions longer than 64b
We don't support instructions longer than 64-bits yet. Still, we can
modify validate_riscv_insn function to prevent unexpected behavior by
limiting the "length" of an instruction to 64-bit (or less).
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Fix function
description comment based on current spec. Limit instruction
length up to 64-bit for now. Make sure that required_bits does
not corrupt even if unsigned long long is longer than 64-bit.
Diffstat (limited to 'gdb/disasm.h')
0 files changed, 0 insertions, 0 deletions