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| author | Luis Machado <luis.machado@linaro.org> | 2021-10-04 13:56:43 -0300 |
|---|---|---|
| committer | Luis Machado <luis.machado@linaro.org> | 2021-10-11 16:03:52 -0300 |
| commit | ecbf5d4f9b716c50908f62cbb9917ed42d45a254 (patch) | |
| tree | 324ced2777be84902c17eed80ae86802d15fbb88 /gdb/arch | |
| parent | dc22c61a1600639046407fb171613a3192fc0608 (diff) | |
| download | fsf-binutils-gdb-ecbf5d4f9b716c50908f62cbb9917ed42d45a254.zip fsf-binutils-gdb-ecbf5d4f9b716c50908f62cbb9917ed42d45a254.tar.gz fsf-binutils-gdb-ecbf5d4f9b716c50908f62cbb9917ed42d45a254.tar.bz2 | |
[ARM] Refactor pseudo register numbering
The pseudo register handling for ARM uses some hardcoded constants to
determine types and names. In preparation to the upcoming MVE support
patch (that will add another pseudo register), this patch refactors and
reorganizes things in order to simplify handling of future pseudo registers.
We keep track of the first pseudo register number in a group and the number of
pseudo registers in that group.
Right now we only have the S and Q pseudo registers.
Diffstat (limited to 'gdb/arch')
0 files changed, 0 insertions, 0 deletions