aarch64: Add support for sve2p1 orqv instruction.

This patch adds support for SVE2p1 "orqv" instruction, spec available here [1].
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en

5 files changed, 64 insertions, 0 deletions

diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
new file mode 100644
index 0000000..d28b059
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.d
@@ -0,0 +1,3 @@
+#name: Test of illegal SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#error_output: sve2p1-5-invalid.l
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
new file mode 100644
index 0000000..4cd7502
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.l
@@ -0,0 +1,27 @@
+.*: Assembler messages:
+.*: Error: operand mismatch -- `orqv v0.8h,p0,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.16b, p0, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.8h, p0, z0.h
+.*: Info:    	orqv v0.4s, p0, z0.s
+.*: Info:    	orqv v0.2d, p0, z0.d
+.*: Error: p0-p7 expected at operand 2 -- `orqv v31.16b,p8,z0.b'
+.*: Error: operand mismatch -- `orqv v0.2d,p7,z0.b'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.16b, p7, z0.b
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.8h, p7, z0.h
+.*: Info:    	orqv v0.4s, p7, z0.s
+.*: Info:    	orqv v0.2d, p7, z0.d
+.*: Error: bad vector arrangement type at operand 1 -- `orqv v0.2b,p7,z0.b'
+.*: Error: indexed vector register expected at operand 1 -- `orqv v0.b,p0,z0.16b'
+.*: Error: unexpected character `8' in element size at operand 3 -- `orqv v0.4h,p0,z0.8h'
+.*: Error: unexpected character `4' in element size at operand 3 -- `orqv v0.4s,p8/m,z0.4s'
+.*: Error: operand mismatch -- `orqv v0.2d,p0/z,z0.d'
+.*: Info:    did you mean this\?
+.*: Info:    	orqv v0.2d, p0, z0.d
+.*: Info:    other valid variant\(s\):
+.*: Info:    	orqv v0.16b, p0, z0.b
+.*: Info:    	orqv v0.8h, p0, z0.h
+.*: Info:    	orqv v0.4s, p0, z0.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
new file mode 100644
index 0000000..36edb87
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5-invalid.s
@@ -0,0 +1,8 @@
+orqv v0.8h, p0, z0.b
+orqv v31.16b, p8, z0.b
+orqv v0.2d, p7, z0.b
+orqv v0.2b, p7, z0.b
+orqv v0.b, p0, z0.16b
+orqv v0.4h, p0, z0.8h
+orqv v0.4s, p8/m, z0.4s
+orqv v0.2d, p0/z, z0.d
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.d b/gas/testsuite/gas/aarch64/sve2p1-5.d
new file mode 100644
index 0000000..f581e34
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.d
@@ -0,0 +1,18 @@
+#name: Test of SVE2.1 orqv instruction.
+#as: -march=armv9.4-a
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	041c2000 	orqv	v0.16b, p0, z0.b
+.*:	041c201f 	orqv	v31.16b, p0, z0.b
+.*:	04dc2000 	orqv	v0.2d, p0, z0.d
+.*:	041c3c00 	orqv	v0.16b, p7, z0.b
+.*:	041c23e0 	orqv	v0.16b, p0, z31.b
+.*:	04dc3fff 	orqv	v31.2d, p7, z31.d
+.*:	045c35ef 	orqv	v15.8h, p5, z15.h
+.*:	049c2e8a 	orqv	v10.4s, p3, z20.s
diff --git a/gas/testsuite/gas/aarch64/sve2p1-5.s b/gas/testsuite/gas/aarch64/sve2p1-5.s
new file mode 100644
index 0000000..12f0b85
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p1-5.s
@@ -0,0 +1,8 @@
+orqv v0.16b, p0, z0.b
+orqv v31.16b, p0, z0.b
+orqv v0.2d, p0, z0.d
+orqv v0.16b, p7, z0.b
+orqv v0.16b, p0, z31.b
+orqv v31.2d, p7, z31.d
+orqv v15.8h, p5, z15.h
+orqv v10.4s, p3, z20.s