bfd/

	* configure.in (bfd_elf32_bigarm_vec): Include elf-vxworks.lo.
	(bfd_elf32_bigarm_symbian_vec): Likewise.
	(bfd_elf32_bigarm_vxworks_vec): Likewise.
	(bfd_elf32_littlearm_vec): Likewise.
	(bfd_elf32_littlearm_symbian_vec): Likewise.
	(bfd_elf32_littlearm_vxworks_vec): Likewise.
	* configure: Regenerate.
	* elf32-arm.c: Include libiberty.h and elf-vxworks.h.
	(RELOC_SECTION, RELOC_SIZE, SWAP_RELOC_IN, SWAP_RELOC_OUT): New macros.
	(elf32_arm_vxworks_bed): Add forward declaration.
	(elf32_arm_howto_table_1): Fix the masks for R_ASM_ABS12.
	(elf32_arm_vxworks_exec_plt0_entry): New table.
	(elf32_arm_vxworks_exec_plt_entry): Likewise.
	(elf32_arm_vxworks_shared_plt_entry): Likewise.
	(elf32_arm_link_hash_table): Add vxworks_p and srelplt2 fields.
	(reloc_section_p): New function.
	(create_got_section): Use RELOC_SECTION.
	(elf32_arm_create_dynamic_sections): Likewise.  Call
	elf_vxworks_create_dynamic_sections for VxWorks targets.
	Choose between the two possible values of plt_header_size
	and plt_entry_size.
	(elf32_arm_link_hash_table_create): Initialize vxworks_p and srelplt2.
	(elf32_arm_abs12_reloc): New function.
	(elf32_arm_final_link_relocate): Call it.  Allow the creation of
	dynamic R_ARM_ABS12 relocs on VxWorks.  Use reloc_section_p,
	RELOC_SIZE, SWAP_RELOC_OUT and RELOC_SECTION.  Initialize the
	r_addend fields of relocs.  On rela targets, skip any code that
	adjusts in-place addends.  When using _bfd_link_final_relocate
	to perform a final relocation, pass rel->r_addend as the addend
	argument.
	(elf32_arm_merge_private_bfd_data): If one of the bfds is a VxWorks
	object, ignore flags that are not standard on VxWorks.
	(elf32_arm_check_relocs): Allow the creation of dynamic R_ARM_ABS12
	relocs on VxWorks.  Use reloc_section_p.
	(elf32_arm_adjust_dynamic_symbol): Use RELOC_SECTION and RELOC_SIZE.
	(allocate_dynrelocs): Use RELOC_SIZE.  Account for the size of
	.rela.plt.unloaded relocs on VxWorks targets.
	(elf32_arm_size_dynamic_sections): Use RELOC_SIZE.  Check for
	.rela.plt.unloaded as well as .rel(a).plt.  Add DT_RELA* tags
	instead of DT_REL* tags on RELA targets.
	(elf32_arm_finish_dynamic_symbol): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle VxWorks
	PLT entries.  Do not make _GLOBAL_OFFSET_TABLE_ absolute on VxWorks.
	(elf32_arm_finish_dynamic_sections): Use RELOC_SECTION, RELOC_SIZE
	and SWAP_RELOC_OUT.  Initialize r_addend fields.  Handle DT_RELASZ
	like DT_RELSZ.  Handle the VxWorks form of initial PLT entry.
	Correct the .rela.plt.unreloaded symbol indexes.
	(elf32_arm_output_symbol_hook): Call the VxWorks version of this
	hook on VxWorks targets.
	(elf32_arm_vxworks_link_hash_table_create): Set vxworks_p to true.
	Minor formatting tweak.
	(elf32_arm_vxworks_final_write_processing): New function.
	(elf_backend_add_symbol_hook): Override for VxWorks and reset
	for Symbian.
	(elf_backend_final_write_processing): Likewise.
	(elf_backend_emit_relocs): Likewise.
	(elf_backend_want_plt_sym): Likewise.
	(ELF_MAXPAGESIZE): Likewise.
	(elf_backend_may_use_rel_p): Minor formatting tweak.
	(elf_backend_may_use_rela_p): Likewise.
	(elf_backend_default_use_rela_p): Likewise.
	(elf_backend_rela_normal): Likewise.
	* Makefile.in (elf32-arm.lo): Depend on elf-vxworks.h.

gas/
	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
	R_ARM_ABS12 reloc.
	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.

gas/testsuite/
	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
	* gas/arm/pic.d: Skip for *-*-vxworks*...
	* gas/arm/pic_vxworks.d: ...use this version instead.
	* gas/arm/unwind_vxworks.d: Fix expected output.

ld/
	* emulparams/armelf_vxworks.sh: Include vxworks.sh.
	(MAXPAGESIZE): Define.
	* emulparams/vxworks.sh: Undefine.
	* Makefile.am (earmelf_vxworks.c): Depend on vxworks.sh and vxworks.em.
	* Makefile.in: Regenerate.

ld/testsuite/
	* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
	* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
	* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
	* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
	* ld-arm/vxworks2-static.sd: New tests.
	* ld-arm/arm-elf.exp: Run them.

8 files changed, 101 insertions, 17 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index ca185b1..5417f7e 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,18 @@
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Zack Weinberg  <zack@codesourcery.com>
+	    Nathan Sidwell  <nathan@codesourcery.com>
+	    Paul Brook  <paul@codesourcery.com>
+	    Ricardo Anguiano  <anguiano@codesourcery.com>
+	    Phil Edwards  <phil@codesourcery.com>
+
+	* config/tc-arm.c (md_apply_fix): Install a value of zero into a
+	BFD_RELOC_ARM_OFFSET_IMM field if we're going to generate a RELA
+	R_ARM_ABS12 reloc.
+	(tc_gen_reloc): Keep the original fx_offset for RELA pc-relative
+	relocs, but adjust by md_pcrel_from_section.  Create R_ARM_ABS12
+	relocations for BFD_RELOC_ARM_OFFSET_IMM on RELA targets.
+
 2006-03-06  Bob Wilson  <bob.wilson@acm.org>
 
 	* config/tc-xtensa.c (xtensa_post_relax_hook): Generate literal tables
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 79da171..e98733d 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11535,6 +11535,9 @@ md_apply_fix (fixS *	fixP,
       break;
 
     case BFD_RELOC_ARM_OFFSET_IMM:
+      if (!fixP->fx_done && seg->use_rela_p)
+	value = 0;
+
     case BFD_RELOC_ARM_LITERAL:
       sign = value >= 0;
 
@@ -12256,8 +12259,7 @@ md_apply_fix (fixS *	fixP,
    format.  */
 
 arelent *
-tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
-	      fixS *	 fixp)
+tc_gen_reloc (asection *section, fixS *fixp)
 {
   arelent * reloc;
   bfd_reloc_code_real_type code;
@@ -12269,7 +12271,12 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
 
   if (fixp->fx_pcrel)
-    fixp->fx_offset = reloc->address;
+    {
+      if (section->use_rela_p)
+	fixp->fx_offset -= md_pcrel_from_section (fixp, section);
+      else
+	fixp->fx_offset = reloc->address;
+    }
   reloc->addend = fixp->fx_offset;
 
   switch (fixp->fx_r_type)
@@ -12357,6 +12364,12 @@ tc_gen_reloc (asection * section ATTRIBUTE_UNUSED,
       return NULL;
 
     case BFD_RELOC_ARM_OFFSET_IMM:
+      if (section->use_rela_p)
+	{
+	  code = fixp->fx_r_type;
+	  break;
+	}
+
       if (fixp->fx_addsy != NULL
 	  && !S_IS_DEFINED (fixp->fx_addsy)
 	  && S_IS_LOCAL (fixp->fx_addsy))
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 28adf50..2eb5dbc 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+
+	* gas/arm/abs12.s, gas/arm/abs12.d: New test.
+	* gas/arm/pic.d: Skip for *-*-vxworks*...
+	* gas/arm/pic_vxworks.d: ...use this version instead.
+	* gas/arm/unwind_vxworks.d: Fix expected output.
+
 2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* gas/m68k/arch-cpu-1.s: Tweak.
diff --git a/gas/testsuite/gas/arm/abs12.d b/gas/testsuite/gas/arm/abs12.d
new file mode 100644
index 0000000..5d4bb3b
--- /dev/null
+++ b/gas/testsuite/gas/arm/abs12.d
@@ -0,0 +1,20 @@
+#objdump: -dr
+#not-skip: *-vxworks
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+00000000 <\.text>:
+   0:	e5910000 	ldr	r0, \[r1\]
+			0: R_ARM_ABS12	global
+   4:	e5910000 	ldr	r0, \[r1\]
+			4: R_ARM_ABS12	global\+0xc
+   8:	e5910000 	ldr	r0, \[r1\]
+			8: R_ARM_ABS12	global\+0x100000
+   c:	e5910000 	ldr	r0, \[r1\]
+			c: R_ARM_ABS12	\.text\+0x18
+  10:	e5910000 	ldr	r0, \[r1\]
+			10: R_ARM_ABS12	\.text\+0x24
+  14:	e5910000 	ldr	r0, \[r1\]
+			14: R_ARM_ABS12	\.text\+0x100018
diff --git a/gas/testsuite/gas/arm/abs12.s b/gas/testsuite/gas/arm/abs12.s
new file mode 100644
index 0000000..9c2faa5
--- /dev/null
+++ b/gas/testsuite/gas/arm/abs12.s
@@ -0,0 +1,7 @@
+	ldr	r0,[r1,#global]
+	ldr	r0,[r1,#global + 12]
+	ldr	r0,[r1,#global + 0x100000]
+	ldr	r0,[r1,#local]
+	ldr	r0,[r1,#local + 12]
+	ldr	r0,[r1,#local + 0x100000]
+local:
diff --git a/gas/testsuite/gas/arm/pic.d b/gas/testsuite/gas/arm/pic.d
index 8eed71d..f5232a3 100644
--- a/gas/testsuite/gas/arm/pic.d
+++ b/gas/testsuite/gas/arm/pic.d
@@ -2,6 +2,8 @@
 #name: PIC
 # This test is only valid on ELF based ports.
 #not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+# VxWorks needs a special variant of this file.
+#skip: *-*-vxworks*
 
 # Test generation of PIC
 
diff --git a/gas/testsuite/gas/arm/pic_vxworks.d b/gas/testsuite/gas/arm/pic_vxworks.d
new file mode 100644
index 0000000..f7db8aa
--- /dev/null
+++ b/gas/testsuite/gas/arm/pic_vxworks.d
@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: PIC
+#source: pic.s
+#not-skip: *-*-vxworks*
+
+# Test generation of PIC
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+00+0 <[^>]*> eb000000 	bl	.*
+			0: R_ARM_PC24	foo\+0xfffffff8
+00+4 <[^>]*> eb000000 	bl	.*
+			4: R_ARM_PLT32	foo\+0xfffffff8
+	\.\.\.
+			8: R_ARM_ABS32	sym
+			c: R_ARM_GOT32	sym
+			10: R_ARM_GOTOFF32	sym
+			14: R_ARM_GOTPC	_GLOBAL_OFFSET_TABLE_
+			18: R_ARM_TARGET1	foo2
+			1c: R_ARM_SBREL32	foo3
+			20: R_ARM_TARGET2	foo4
diff --git a/gas/testsuite/gas/arm/unwind_vxworks.d b/gas/testsuite/gas/arm/unwind_vxworks.d
index 333e6ce..ccd16a6 100644
--- a/gas/testsuite/gas/arm/unwind_vxworks.d
+++ b/gas/testsuite/gas/arm/unwind_vxworks.d
@@ -1,7 +1,5 @@
 #objdump: -sr
 #name: Unwind table generation
-# This test is only valid on ELF based ports.
-#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
 # This is the VxWorks variant of this file.
 #source: unwind.s
 #not-skip: *-*-vxworks*
@@ -10,22 +8,22 @@
 
 RELOCATION RECORDS FOR \[.ARM.extab\]:
 OFFSET   TYPE              VALUE 
-0000000c R_ARM_PREL31      .text\+0x0+c
+0000000c R_ARM_PREL31      .text
 
 
 RELOCATION RECORDS FOR \[.ARM.exidx\]:
 OFFSET   TYPE              VALUE 
 00000000 R_ARM_PREL31      .text
 00000000 R_ARM_NONE        __aeabi_unwind_cpp_pr0
-00000008 R_ARM_PREL31      .text.*
-00000008 R_ARM_NONE        __aeabi_unwind_cpp_pr1\+0x0+8
-0000000c R_ARM_PREL31      .ARM.extab\+0x0+c
-00000010 R_ARM_PREL31      .text.*
-00000014 R_ARM_PREL31      .ARM.extab.*
-00000018 R_ARM_PREL31      .text.*
-0000001c R_ARM_PREL31      .ARM.extab.*
-00000020 R_ARM_PREL31      .text.*
-00000028 R_ARM_PREL31      .text.*
+00000008 R_ARM_PREL31      .text.*\+0x00000004
+00000008 R_ARM_NONE        __aeabi_unwind_cpp_pr1
+0000000c R_ARM_PREL31      .ARM.extab
+00000010 R_ARM_PREL31      .text.*\+0x00000008
+00000014 R_ARM_PREL31      .ARM.extab.*\+0x0000000c
+00000018 R_ARM_PREL31      .text.*\+0x0000000c
+0000001c R_ARM_PREL31      .ARM.extab.*\+0x0000001c
+00000020 R_ARM_PREL31      .text.*\+0x00000010
+00000028 R_ARM_PREL31      .text.*\+0x00000012
 
 
 Contents of section .text:
@@ -36,8 +34,8 @@ Contents of section .ARM.extab:
  0010 (8402b101 b0b0b005 2a000000 00c60181|01b10284 05b0b0b0 0000002a 8101c600)  .*
  0020 (b0b0c1c1|c1c1b0b0) 00000000                    .*
 Contents of section .ARM.exidx:
- 0000 00000000 (b0b0a880 00000000|80a8b0b0 00000000) 00000000  .*
+ 0000 00000000 (b0b0a880|80a8b0b0) 00000000 00000000  .*
  0010 00000000 00000000 00000000 00000000  .*
- 0020 (00000000 08849780 00000000 b00fb180|00000000 80978408 00000000 80b10fb0)  .*
+ 0020 00000000 (08849780|80978408) 00000000 (b00fb180|80b10fb0)  .*
 # Ignore .ARM.attributes section
 #...