* configure.in (crisv32): Recognize. AC_DEFINE_UNQUOTED

	DEFAULT_CRIS_ARCH.  Handle crisv32-*-linux-gnu* like
	cris-*-linux-gnu* and crisv32-*-* like cris-*-*.
	* configure: Regenerate.
	* config/tc-cris.c (enum cris_archs): New.
	(cris_mach, cris_arch_from_string, s_cris_arch, get_sup_reg)
	(cris_insn_ver_valid_for_arch): New functions.
	(DEFAULT_CRIS_ARCH): New macro, default to cris_any_v0_v10.
	(cris_arch): New variable.
	(md_pseudo_table): New pseudo .arch.
	(err_for_dangerous_mul_placement): Initialize according to
	DEFAULT_CRIS_ARCH.
	(STATE_COND_BRANCH): Renamed from STATE_CONDITIONAL_BRANCH.
	All users changed.
	(STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON)
	(STATE_ABS_BRANCH_V32, STATE_LAPC, BRANCH_BF_V32, BRANCH_BB_V32)
	(BRANCH_WF_V32, BRANCH_WB_V32): New.
	(BRANCH_BF, BRANCH_BB, BRANCH_WF, BRANCH_WB): Don't undef after
	use in md_cris_relax_table.
	(md_cris_relax_table): Add entries for STATE_COND_BRANCH_V32,
	STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
	Update and improve head comment.
	(OPTION_PIC): Define in terms of previous option, OPTION_US.
	(OPTION_MULBUG_ABORT_ON, OPTION_MULBUG_ABORT_OFF): Similar.
	(OPTION_ARCH): New.
	(md_longopts): New option --march=...
	(cris_any_v0_v10_long_jump_size, crisv32_long_jump_size): New
	macros.
	(md_long_jump_size): Initialize in terms of DEFAULT_CRIS_ARCH.
	(HANDLE_RELAXABLE): New macro.
	(md_estimate_size_before_relax): Use HANDLE_RELAXABLE for common
	cases.  Check for weak symbols and assume not relaxable.  Handle
	STATE_COND_BRANCH_V32, STATE_COND_BRANCH_COMMON,
	STATE_ABS_BRANCH_V32, STATE_LAPC.  Use new variable symbolP, not
	fragP->fr_symbol.
	(md_convert_frag): Handle STATE_COND_BRANCH_V32,
	STATE_COND_BRANCH_COMMON, STATE_ABS_BRANCH_V32, STATE_LAPC.
	(cris_create_short_jump): Adjust for CRISv32.
	(md_create_long_jump): Ditto.  Emit error for common_v10_v32.
	(md_begin): Define symbols "..asm.arch.cris.v32",
	"..asm.arch.cris.v10", "..asm.arch.cris.common_v10_v32" and
	"..asm.arch.cris.any_v0_v10".  Use cris_insn_ver_valid_for_arch
	when entering opcode table entry points.
	(md_assemble): Adjust branch handling for CRISv32.  Handle LAPC
	relaxation.  In fix_new_exp call for main insn, pass 1 for pcrel
	parameter for 8, 16 and 32-bit pc-relative insns and LAPC.
	(cris_process_instruction): Initialize out_insnp->insn_type to
	CRIS_INSN_NONE, not CRIS_INSN_NORMAL.
	<case ']', '[', 'A', 'd', 'Q', 'N', 'n', 'Y', 'U', 'u', 'T'>: New
	cases.
	<case 'm'>: Check that modified_char == '.'.
	<invalid operands>: Consume the rest of the line.
	When operands don't match, skip over subsequent insns with
	non-matching version specifier but same mnemonic.
	<immediate constant, case SIZE_SPEC_REG>: Immediate operands for
	special registers in CRISv32 are always 32 bit long.
	<immediate constant, case SIZE_FIELD_SIGNED, SIZE_FIELD_UNSIGNED>:
	New cases.
	(get_gen_reg): Only recognize "PC" when followed by "+]" for v32
	and compatible.  Recognize "ACR" for v32, unless followed by "+".
	(get_spec_reg): Consider cris_arch when looking up register.
	(get_autoinc_prefix_or_indir_op): Don't recognize assignment for
	v32 or compatible.
	(get_3op_or_dip_prefix_op): Check for ']' after seeing '[rN+'.
	(cris_get_expression): Restore input_line_pointer if failing "early".
	(get_flags): Consider cris_arch and recognize flags accordingly.
	(branch_disp): Adjust for CRISv32.
	(gen_cond_branch_32): Similar.  Emit error for common_v10_v32.
	(cris_number_to_imm): Use as_bad_where, not as_bad.  Remove
	related FIXME.  Don't insist on BFD_RELOC_32_PCREL fixup to be
	resolved.  Don't enter zeros in object file for
	BFD_RELOC_32_PCREL.
	<case BFD_RELOC_CRIS_LAPCQ_OFFSET, BFD_RELOC_CRIS_SIGNED_16>
	<case BFD_RELOC_CRIS_SIGNED_8>: New case.
	(md_parse_option): Break out "return 1".
	<OPTION_ARCH> New case.
	(tc_gen_reloc): <case BFD_RELOC_CRIS_LAPCQ_OFFSET>
	<case BFD_RELOC_CRIS_SIGNED_16, BFD_RELOC_CRIS_SIGNED_8>
	<case BFD_RELOC_CRIS_UNSIGNED_8, BFD_RELOC_CRIS_UNSIGNED_16>
	<case BFD_RELOC_32_PCREL>: New cases.
	Addends for non-zero fx_pcrel are too in fx_offset.
	(md_show_usage): Show --march=<arch>.
	(md_apply_fix3): Adjust val for BFD_RELOC_CRIS_LAPCQ_OFFSET.
	(md_pcrel_from): BFD_RELOC_CRIS_LAPCQ_OFFSET is PC-relative too.
	(s_syntax) <struct syntaxes>: Properly constify member operand.
	* config/tc-cris.h (TARGET_MACH): Define.
	(cris_mach): Declare.
	* doc/as.texinfo (Overview) <CRIS>: Add --march=...
	* doc/c-cris.texi (CRIS-Symbols): New node for built-in symbols.
	(CRIS-Opts): Document --march=...
	(CRIS-Pseudos): Document .arch.

1 files changed, 100 insertions, 2 deletions

diff --git a/gas/doc/c-cris.texi b/gas/doc/c-cris.texi
index e814767..e84952c 100644
--- a/gas/doc/c-cris.texi
+++ b/gas/doc/c-cris.texi
@@ -16,6 +16,7 @@
 @menu
 * CRIS-Opts::              Command-line Options
 * CRIS-Expand::            Instruction expansion
+* CRIS-Symbols::           Symbols
 * CRIS-Syntax::            Syntax
 @end menu
 
@@ -68,6 +69,39 @@ affect expansion of instructions.  The expansion with
 @option{--pic} will use PC-relative rather than (slightly
 faster) absolute addresses in those expansions.
 
+@cindex @option{--march=@var{architecture}} command line option, CRIS
+@cindex CRIS @option{--march=@var{architecture}} command line option
+@cindex Architecture variant option, CRIS
+@cindex CRIS architecture variant option
+The option @option{--march=@var{architecture}}
+@anchor{march-option}specifies the recognized instruction set
+and recognized register names.  It also controls the
+architecture type of the object file.  Valid values for
+@var{architecture} are:
+@table @code
+
+@item v0_v10
+All instructions and register names for any architecture variant
+in the set v0@dots{}v10 are recognized.  This is the
+default if the target is configured as cris-*.
+
+@item v10
+Only instructions and register names for CRIS v10 (as found in
+ETRAX 100 LX) are recognized.  This is the default if the target
+is configured as crisv10-*.
+
+@item v32
+Only instructions and register names for CRIS v32 (code name
+Guinness) are recognized.  This is the default if the target is
+configured as crisv32-*.  This value implies
+@option{--no-mul-bug-abort}.  (A subsequent
+@option{--mul-bug-abort} will turn it back on.)
+
+@item common_v10_v32
+Only instructions with register names and addressing modes with
+opcodes common to the v10 and v32 are recognized.
+@end table
+
 @cindex @option{-N} command line option, CRIS
 @cindex CRIS @option{-N} command line option
 When @option{-N} is specified, @code{@value{AS}} will emit a
@@ -113,6 +147,59 @@ full 32-bit address.  Since this does not correspond to a single
 instruction, such expansions can optionally be warned about.
 @xref{CRIS-Opts}.
 
+If the operand is found to fit the range, a @code{lapc} mnemonic
+will translate to a @code{lapcq} instruction.  Use @code{lapc.d}
+to force the 32-bit @code{lapc} instruction.
+
+Similarly, the @code{addo} mnemonic will translate to the
+shortest fitting instruction of @code{addoq}, @code{addo.w} and
+@code{addo.d}, when used with a operand that is a constant known
+at assembly time.
+
+@node CRIS-Symbols
+@section Symbols
+@cindex Symbols, built-in, CRIS
+@cindex Symbols, CRIS, built-in
+@cindex CRIS built-in symbols
+@cindex Built-in symbols, CRIS
+
+Some symbols are defined by the assembler.  They're intended to
+be used in conditional assembly, for example:
+@smallexample
+ .if ..asm.arch.cris.v32
+ @var{code for CRIS v32}
+ .elseif ..asm.arch.cris.common_v10_v32
+ @var{code common to CRIS v32 and CRIS v10}
+ .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10
+ @var{code for v10}
+ .else
+ .error "Code needs to be added here."
+ .endif
+@end smallexample
+
+These symbols are defined in the assembler, reflecting
+command-line options, either when specified or the default.
+They are always defined, to 0 or 1.
+@table @code
+
+@item ..asm.arch.cris.any_v0_v10
+This symbol is non-zero when @option{--march=v0_v10} is specified
+or the default.
+
+@item ..asm.arch.cris.common_v10_v32
+Set according to the option @option{--march=common_v10_v32}.
+
+@item ..asm.arch.cris.v10
+Reflects the option @option{--march=v10}.
+
+@item ..asm.arch.cris.v32
+Corresponds to @option{--march=v10}.
+@end table
+
+Speaking of symbols, when a symbol is used in code, it can have
+a suffix modifying its value for use in position-independent
+code. @xref{CRIS-Pic}.
+
 @node CRIS-Syntax
 @section Syntax
 
@@ -147,7 +234,8 @@ separate instructions can be specified on a single line.
 @cindex Position-independent code, symbols in, CRIS
 
 When generating @anchor{crispic}position-independent code (SVR4
-PIC) for use in cris-axis-linux-gnu shared libraries, symbol
+PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu
+shared libraries, symbol
 suffixes are used to specify what kind of run-time symbol lookup
 will be used, expressed in the object as different
 @emph{relocation types}.  Usually, all absolute symbol values
@@ -271,7 +359,7 @@ each expression, a 32-bit little-endian constant is emitted.
 @cindex pseudo-op .syntax, CRIS
 @cindex CRIS assembler directive .syntax
 @cindex CRIS pseudo-op .syntax
-The @code{.syntax} directive takes as ARGUMENT one of the
+The @code{.syntax} directive takes as @var{ARGUMENT} one of the
 following case-sensitive choices.
 
 @table @code
@@ -305,6 +393,16 @@ directive and emits an error if the option @option{--underscore}
 is in effect.
 @end table
 
+@item .arch ARGUMENT
+@cindex assembler directive .arch, CRIS
+@cindex pseudo-op .arch, CRIS
+@cindex CRIS assembler directive .arch
+@cindex CRIS pseudo-op .arch
+This is an assertion directive, giving an error if the specified
+@var{ARGUMENT} is not the same as the specified or default value
+for the @option{--march=@var{architecture}} option
+(@pxref{march-option}).
+
 @c If you compare with md_pseudo_table, you see that we don't
 @c document ".file" and ".loc" here.  This is because we're just
 @c wrapping the corresponding ELF function and emitting an error for