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author | Jim Wilson <jimw@sifive.com> | 2017-12-01 15:34:42 -0800 |
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committer | Jim Wilson <jimw@sifive.com> | 2017-12-01 15:34:42 -0800 |
commit | b57e49f726f854e65b2ce5e87dc7ee664daac1fb (patch) | |
tree | 4336e43eb4dcec86eeac5950bf10589d29390bb6 /gas/doc/as.texinfo | |
parent | 40fc416f4e22913ba2a2bafcc8da05f59c677b7d (diff) | |
download | fsf-binutils-gdb-b57e49f726f854e65b2ce5e87dc7ee664daac1fb.zip fsf-binutils-gdb-b57e49f726f854e65b2ce5e87dc7ee664daac1fb.tar.gz fsf-binutils-gdb-b57e49f726f854e65b2ce5e87dc7ee664daac1fb.tar.bz2 |
Update and clean up RISC-V gas documentation.
gas/
* doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change
RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic
and related options to option list.
* doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts.
(RISC-V Options): Renamed from Options. Add missing period.
(-fpic): Also mention -fPIC.
(RISC-V Directives): New node.
Diffstat (limited to 'gas/doc/as.texinfo')
-rw-r--r-- | gas/doc/as.texinfo | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index d37a1d6..faa228d 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -502,6 +502,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mnolink-relax}] [@b{-mno-warn-regname-label}] @end ifset +@ifset RISCV + +@emph{Target RISC-V options:} + [@b{-fpic}|@b{-fPIC}|@b{-fno-pic}] + [@b{-march}=@var{ISA}] + [@b{-mabi}=@var{ABI}] +@end ifset @ifset RL78 @emph{Target RL78 options:} @@ -520,12 +527,6 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-mint-register=@var{number}}] [@b{-mgcc-abi}|@b{-mrx-abi}] @end ifset -@ifset RISCV - -@emph{Target RISC-V options:} - [@b{-march}=@var{ISA}] - [@b{-mabi}=@var{ABI}] -@end ifset @ifset S390 @emph{Target s390 options:} @@ -1702,14 +1703,14 @@ PowerPC processor. @ifset RISCV @ifclear man -@xref{RISC-V-Opts}, for the options available when @value{AS} is configured +@xref{RISC-V-Options}, for the options available when @value{AS} is configured for a RISC-V processor. @end ifclear @ifset man @c man begin OPTIONS The following options are available when @value{AS} is configured for a -RISC-V processor. +RISC-V processor. @c man end @c man begin INCLUDE @include c-riscv.texi @@ -7710,12 +7711,12 @@ subject, see the hardware manufacturer's manual. @ifset PRU * PRU-Dependent:: PRU Dependent Features @end ifset -@ifset RL78 -* RL78-Dependent:: RL78 Dependent Features -@end ifset @ifset RISCV * RISC-V-Dependent:: RISC-V Dependent Features @end ifset +@ifset RL78 +* RL78-Dependent:: RL78 Dependent Features +@end ifset @ifset RX * RX-Dependent:: RX Dependent Features @end ifset @@ -7946,14 +7947,14 @@ family. @include c-pru.texi @end ifset -@ifset RL78 -@include c-rl78.texi -@end ifset - @ifset RISCV @include c-riscv.texi @end ifset +@ifset RL78 +@include c-rl78.texi +@end ifset + @ifset RX @include c-rx.texi @end ifset |