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| author | Tejas Joshi <TejasSanjay.Joshi@amd.com> | 2022-11-15 21:56:37 +0530 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2022-11-15 10:07:02 -0800 |
| commit | b0e8fa7ff0dc9a32ff71df0e895aa7fb5089fcfa (patch) | |
| tree | 6a0f801be0b037087fc7a45033a4bb927ab4aad1 /gas/config | |
| parent | 7e21379963c8be351a03693ce64d0a597ea0dbd7 (diff) | |
| download | fsf-binutils-gdb-b0e8fa7ff0dc9a32ff71df0e895aa7fb5089fcfa.zip fsf-binutils-gdb-b0e8fa7ff0dc9a32ff71df0e895aa7fb5089fcfa.tar.gz fsf-binutils-gdb-b0e8fa7ff0dc9a32ff71df0e895aa7fb5089fcfa.tar.bz2 | |
Add AMD znver4 processor support
2022-09-28 Tejas Joshi <TejasSanjay.Joshi@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Add znver4 ARCH and rmpquery SUBARCH.
(md_assemble): Expand comment before swap_operands() with rmpquery.
* doc/c-i386.texi: Add znver4.
* testsuite/gas/i386/arch-14-1.d: New.
* testsuite/gas/i386/arch-14-1.s: New.
* testsuite/gas/i386/arch-14-znver4.d: New.
* testsuite/gas/i386/i386.exp: Add new znver4 test cases.
* testsuite/gas/i386/rmpquery.d: New.
* testsuite/gas/i386/rmpquery.s: New.
* testsuite/gas/i386/x86-64-arch-4-1.d: New.
* testsuite/gas/i386/x86-64-arch-4-1.s: New.
* testsuite/gas/i386/x86-64-arch-4-znver4.d: New.
opcodes/
* i386-dis.c (x86_64_table): Add rmpquery.
* i386-gen.c (cpu_flag_init): Add CPU_ZNVER4_FLAGS and
CPU_RMPQUERY_FLAGS.
(cpu_flags): Add CpuRMPQUERY.
* i386-opc.h (enum): Add CpuRMPQUERY.
(i386_cpu_flags): Add cpurmpquery.
* i386-opc.tbl: Add rmpquery insn.
* i386-init.h: Re-generated.
* i386-tbl.h: Re-generated.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-i386.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 71437d4..a5ea9b1 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -978,6 +978,7 @@ static const arch_entry cpu_arch[] = ARCH (znver1, ZNVER, ZNVER1, false), ARCH (znver2, ZNVER, ZNVER2, false), ARCH (znver3, ZNVER, ZNVER3, false), + ARCH (znver4, ZNVER, ZNVER4, false), ARCH (btver1, BT, BTVER1, false), ARCH (btver2, BT, BTVER2, false), @@ -1106,6 +1107,7 @@ static const arch_entry cpu_arch[] = SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false), + SUBARCH (rmpquery, RMPQUERY, RMPQUERY, false), }; #undef SUBARCH @@ -4875,9 +4877,10 @@ md_assemble (char *line) /* All Intel opcodes have reversed operands except for "bound", "enter", "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", - "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp" - and "call" instructions with 2 immediate operands so that the immediate - segment precedes the offset consistently in Intel and AT&T modes. */ + "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse + intersegment "jmp" and "call" instructions with 2 immediate operands so + that the immediate segment precedes the offset consistently in Intel and + AT&T modes. */ if (intel_syntax && i.operands > 1 && (strcmp (mnemonic, "bound") != 0) |