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authorJan Beulich <jbeulich@suse.com>2024-06-21 08:33:57 +0200
committerJan Beulich <jbeulich@suse.com>2024-06-21 08:33:57 +0200
commitc68a6e5cadf333ab3d55443d3aed156415660600 (patch)
treed25843883605edd98036277430b579540de209fe /gas/config/tc-i386.c
parent4ad2348edbf43a3d1a694fd5375680cb55e6b1c1 (diff)
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x86: don't suppress errors when optimizing
Blindly ignoring any mnemonic suffix can't be quite right: Bad suffix / operand combinations still want flagging. Simply avoid optimizing in such situations.
Diffstat (limited to 'gas/config/tc-i386.c')
-rw-r--r--gas/config/tc-i386.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index b8fc3c4..b8911c0 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4573,6 +4573,20 @@ check_hle (void)
}
}
+/* Helper for optimization (running ahead of process_suffix()), to make sure we
+ convert only well-formed insns. @OP is the sized operand to cross check
+ against (typically a register). Checking against a single operand typically
+ suffices, as match_template() has already honored CheckOperandSize. */
+
+static bool is_plausible_suffix (unsigned int op)
+{
+ return !i.suffix
+ || (i.suffix == BYTE_MNEM_SUFFIX && i.types[op].bitfield.byte)
+ || (i.suffix == WORD_MNEM_SUFFIX && i.types[op].bitfield.word)
+ || (i.suffix == LONG_MNEM_SUFFIX && i.types[op].bitfield.dword)
+ || (i.suffix == QWORD_MNEM_SUFFIX && i.types[op].bitfield.qword);
+}
+
/* Encode aligned vector move as unaligned vector move. */
static void
@@ -4758,6 +4772,7 @@ optimize_encoding (void)
&& i.reg_operands == 1
&& i.imm_operands == 1
&& !i.types[1].bitfield.byte
+ && is_plausible_suffix (1)
&& i.op[0].imms->X_op == O_constant
&& fits_in_imm7 (i.op[0].imms->X_add_number))
{
@@ -4768,7 +4783,7 @@ optimize_encoding (void)
if (flag_code == CODE_64BIT || base_regnum < 4)
{
i.types[1].bitfield.byte = 1;
- /* Ignore the suffix. */
+ /* Squash the suffix. */
i.suffix = 0;
/* Convert to byte registers. 8-bit registers are special,
RegRex64 and non-RegRex64 each have 8 registers. */