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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2018-01-09 14:15:00 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2018-01-09 14:21:59 +0000 |
| commit | 91d8b670661883fc0472fd05cf0e54d0e357c187 (patch) | |
| tree | b5301faacc52bb5d5c67e2e99f31ba20052e5898 /gas/config/tc-arm.c | |
| parent | be2e7d95414eb78f29312f30e62d4cabd55f9fda (diff) | |
| download | fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.zip fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.tar.gz fsf-binutils-gdb-91d8b670661883fc0472fd05cf0e54d0e357c187.tar.bz2 | |
[Arm] Add CSDB instruction
CSDB is a new instruction which Arm has defined. As it shares the
encoding space with NOP instructions, it is available from Armv3 in
Arm mode, and Armv6T2 in Thumb mode.
OK? If so, please commit on my behalf as I don't have commit rights
over here.
Thanks, James
---
opcodes/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* arm-dis.c (arm_opcodes): Add csdb.
(thumb32_opcodes): Add csdb.
gas/
2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
* config/tc-arm.c (insns): Add csdb, enable for Armv3 and above
in Arm execution state, and Armv6T2 and above in Thumb execution
state.
* testsuite/gas/arm/csdb.s: New.
* testsuite/gas/arm/csdb.d: New.
* testsuite/gas/arm/thumb2_it_bad.l: Add csdb.
* testsuite/gas/arm/thumb2_it_bad.s: Add csdb.
Diffstat (limited to 'gas/config/tc-arm.c')
| -rw-r--r-- | gas/config/tc-arm.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 85f74a8..0b81c19 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -11275,6 +11275,12 @@ do_t_clz (void) } static void +do_t_csdb (void) +{ + set_it_insn_type (OUTSIDE_IT_INSN); +} + +static void do_t_cps (void) { set_it_insn_type (OUTSIDE_IT_INSN); @@ -19984,6 +19990,15 @@ static const struct asm_opcode insns[] = TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v3 +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + + TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb), + +#undef ARM_VARIANT +#define ARM_VARIANT & arm_ext_v6t2 #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v6t2_v8m TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), |