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| author | Nathan Huckleberry <nhuck@google.com> | 2023-06-30 22:43:40 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:34 -0600 |
| commit | c0a98a853d5ccde35dca20ad5d7cea0a70e16d56 (patch) | |
| tree | 5a5c318686f441523224c6657ee51419069c38ff /bfd | |
| parent | c8cb37347fde3ae12c943c2133a1043eece4c127 (diff) | |
| download | fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.zip fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.gz fsf-binutils-gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.bz2 | |
RISC-V: Add support for the Zvbc extension
Zvbc is part of the crypto vector extensions.
This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbc.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvbc.d: New test.
* testsuite/gas/riscv/zvbc.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
(MASK_VCLMUL_VV): New.
(MATCH_VCLMUL_VX): New.
(MASK_VCLMUL_VX): New.
(MATCH_VCLMULH_VV): New.
(MASK_VCLMULH_VV): New.
(MATCH_VCLMULH_VX): New.
(MASK_VCLMULH_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvbc.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvbc instruction.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 21a4dc8..295e0d2 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1263,6 +1263,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2430,6 +2431,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, || riscv_subset_supports (rps, "zve32f")); case INSN_CLASS_ZVBB: return riscv_subset_supports (rps, "zvbb"); + case INSN_CLASS_ZVBC: + return riscv_subset_supports (rps, "zvbc"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2620,6 +2623,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("v' or `zve64d' or `zve64f' or `zve32f"); case INSN_CLASS_ZVBB: return _("zvbb"); + case INSN_CLASS_ZVBC: + return _("zvbc"); case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: |