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authorRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:48:25 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2016-09-21 16:48:25 +0100
commit8f9a77affe98e0892c46504712a1f0d8372ec765 (patch)
tree728955c70ba36b9372fa7781a3b76c48f7539c32
parentf06935a5c1ef4c978a995361241974917a4ab363 (diff)
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[AArch64][SVE 04/32] Rename neon_type_el to vector_type_el
Similar to the previous patch, but this time for the neon_type_el structure. gas/ * config/tc-aarch64.c (neon_type_el): Rename to... (vector_type_el): ...this. (parse_neon_type_for_operand): Update accordingly. (parse_typed_reg): Likewise. (aarch64_reg_parse): Likewise. (vectype_to_qualifier): Likewise. (parse_operands): Likewise. (eq_neon_type_el): Likewise. Rename to... (eq_vector_type_el): ...this. (parse_neon_reg_list): Update accordingly.
-rw-r--r--gas/ChangeLog13
-rw-r--r--gas/config/tc-aarch64.c32
2 files changed, 29 insertions, 16 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index b66490f..c9e30a1 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,18 @@
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+ * config/tc-aarch64.c (neon_type_el): Rename to...
+ (vector_type_el): ...this.
+ (parse_neon_type_for_operand): Update accordingly.
+ (parse_typed_reg): Likewise.
+ (aarch64_reg_parse): Likewise.
+ (vectype_to_qualifier): Likewise.
+ (parse_operands): Likewise.
+ (eq_neon_type_el): Likewise. Rename to...
+ (eq_vector_type_el): ...this.
+ (parse_neon_reg_list): Update accordingly.
+
+2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
+
* config/tc-aarch64.c (neon_el_type: Rename to...
(vector_el_type): ...this.
(neon_type_el): Update accordingly.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index de1a74d..db30ab4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -86,11 +86,11 @@ enum vector_el_type
NT_q
};
-/* Bits for DEFINED field in neon_type_el. */
+/* Bits for DEFINED field in vector_type_el. */
#define NTA_HASTYPE 1
#define NTA_HASINDEX 2
-struct neon_type_el
+struct vector_type_el
{
enum vector_el_type type;
unsigned char defined;
@@ -747,7 +747,7 @@ aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bfd_boolean
-parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
+parse_neon_type_for_operand (struct vector_type_el *parsed_type, char **str)
{
char *ptr = *str;
unsigned width;
@@ -835,12 +835,12 @@ elt_size:
static int
parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
- struct neon_type_el *typeinfo, bfd_boolean in_reg_list)
+ struct vector_type_el *typeinfo, bfd_boolean in_reg_list)
{
char *str = *ccp;
const reg_entry *reg = parse_reg (&str);
- struct neon_type_el atype;
- struct neon_type_el parsetype;
+ struct vector_type_el atype;
+ struct vector_type_el parsetype;
bfd_boolean is_typed_vecreg = FALSE;
atype.defined = 0;
@@ -955,9 +955,9 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, aarch64_reg_type *rtype,
static int
aarch64_reg_parse (char **ccp, aarch64_reg_type type,
- aarch64_reg_type *rtype, struct neon_type_el *vectype)
+ aarch64_reg_type *rtype, struct vector_type_el *vectype)
{
- struct neon_type_el atype;
+ struct vector_type_el atype;
char *str = *ccp;
int reg = parse_typed_reg (&str, type, rtype, &atype,
/*in_reg_list= */ FALSE);
@@ -974,7 +974,7 @@ aarch64_reg_parse (char **ccp, aarch64_reg_type type,
}
static inline bfd_boolean
-eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
+eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
{
return
e1.type == e2.type
@@ -1003,11 +1003,11 @@ eq_neon_type_el (struct neon_type_el e1, struct neon_type_el e2)
(by reg_list_valid_p). */
static int
-parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
+parse_neon_reg_list (char **ccp, struct vector_type_el *vectype)
{
char *str = *ccp;
int nb_regs;
- struct neon_type_el typeinfo, typeinfo_first;
+ struct vector_type_el typeinfo, typeinfo_first;
int val, val_range;
int in_range;
int ret_val;
@@ -1072,7 +1072,7 @@ parse_neon_reg_list (char **ccp, struct neon_type_el *vectype)
val_range = val;
if (nb_regs == 0)
typeinfo_first = typeinfo;
- else if (! eq_neon_type_el (typeinfo_first, typeinfo))
+ else if (! eq_vector_type_el (typeinfo_first, typeinfo))
{
set_first_syntax_error
(_("type mismatch in vector register list"));
@@ -4631,11 +4631,11 @@ opcode_lookup (char **str)
return NULL;
}
-/* Internal helper routine converting a vector neon_type_el structure
- *VECTYPE to a corresponding operand qualifier. */
+/* Internal helper routine converting a vector_type_el structure *VECTYPE
+ to a corresponding operand qualifier. */
static inline aarch64_opnd_qualifier_t
-vectype_to_qualifier (const struct neon_type_el *vectype)
+vectype_to_qualifier (const struct vector_type_el *vectype)
{
/* Element size in bytes indexed by vector_el_type. */
const unsigned char ele_size[5]
@@ -4988,7 +4988,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
int isreg32, isregzero;
int comma_skipped_p = 0;
aarch64_reg_type rtype;
- struct neon_type_el vectype;
+ struct vector_type_el vectype;
aarch64_opnd_info *info = &inst.base.operands[i];
DEBUG_TRACE ("parse operand %d", i);