Add tile-reset control registers

Add config to hang the serial TL mem off the PBus for the no-L2 case.

Makefile should generate bootrom objdump by default

Add support for tilelink-over-serial

Clock the PeripherySerialAdapter, BlockDevice from the pbus

Bump to July 2020 rocketchip

Bump Rocketchip to June 2020

Align DTB to 8-byte boundary

OpenSBI currently expects the source FDT to be XLEN-aligned when
relocating a copy for the next-stage bootloader or payload, which may
also have similar restrictions.

The devicetree specification advises that the DTB as a whole should be
aligned in memory to the largest alignment of any subblock (8 bytes).

Add constructor and parser for a dramsim ini directory from the cmd line

Dromajo + TraceIO Cleanup

Dromajo Simulation Bridge