- Apr 20, 2023
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Jerry Zhao authored
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- Apr 18, 2023
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Jerry Zhao authored
Use BlockDuringReset to block serial_tl, instead of a async-queue hack
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joonho hwangbo authored
add cstdio to include
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joey0320 authored
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- Apr 11, 2023
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Jerry Zhao authored
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Jerry Zhao authored
* The previous approach used AsyncQueue in a weird way
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- Apr 10, 2023
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Jerry Zhao authored
Add SimTLMem
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joey0320 authored
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joey0320 authored
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joey0320 authored
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- Apr 07, 2023
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Jerry Zhao authored
Bump to latest rocket-chip/chisel3.5.6
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- Mar 21, 2023
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Jerry Zhao authored
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- Mar 18, 2023
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joey0320 authored
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- Mar 09, 2023
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Sagar Karandikar authored
no more binary plusarg
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Sagar Karandikar authored
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- Mar 08, 2023
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Jerry Zhao authored
TSI-over-UART
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Sagar Karandikar authored
fixes for xcelium
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Sagar Karandikar authored
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- Mar 01, 2023
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
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Jerry Zhao authored
Remove TLHelper
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- Feb 23, 2023
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Jerry Zhao authored
People should just construct nodes explicitly. Using TLHelper is a bad pattern, it obscures the actual implementation and provides minimal benefit. It also encourages dependencies on testchipip-as-a-package, which is burdensome to support.
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- Feb 02, 2023
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Jerry Zhao authored
[WIP] Bump to scala 2.13/chisel 3.5.5/latest rocketchip
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