Enable overriding of source ID bits in SerialAdapter

Update Switcher for rocket-chip Feb 14 2019

Add sinkId parameter for integration

Single mBus multi-port switcher support

Helps both top and testharness

Don't do anything special with simserial args

Fesvr handles this now so just pass on the plusargs and
they will be correctly ignored
Fixes #34

Fix periodchecker to not use timescale

Add README

Add prefix to vsrc, csrc and add bootrom to resources

1) Move bootrom and blackboxes to src/main/resources
2) Switch to using HasBlackBoxResource for blackboxes
3) Make build.sbt publishable by adding compile guard for rocketchip
maven dep

Add clock utilities with shells for clock mux, or, and, gater cells (copied from eagle-pll) and add withGatedClock(andReset) objects

Previous assertion was impossible to meet. This will still work assuming you don't create a full loop both on chip and off.

It's currently out of date and can cause casting errors

Scala 2.12 build.sbt fix

Anonymous bundles need it!

Bump to match up with July 3, 2018 Rocket Chip

To detect the presence of other harts in the system, hart 0 sets each
other hart's MSIP and then checks if the bit was successfully written.
However, if that hart somehow clears its own MSIP before the check
occurs, hart 0 will prematurely exit interrupt_loop and fail to bring up
the remaining harts.

This ensures that the other harts do not clear MSIP until hart 0
finishes executing interrupt_loop, which is signaled by hart 0 clearing
its own MSIP.